unixb0y / SystemVerilogSHA256
SHA256 in (System-) Verilog / Open Source FPGA Miner
☆75Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for SystemVerilogSHA256
- A collection of debugging busses developed and presented at zipcpu.com☆36Updated 10 months ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆35Updated 9 months ago
- FPGA reference design for the the Swerv EH1 Core☆67Updated 4 years ago
- Various projects of SPI loader module for xilinx fpga☆25Updated 4 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆84Updated 5 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆79Updated 5 years ago
- JTAG Test Access Port (TAP)☆30Updated 10 years ago
- Verilog implementation of the SHA-512 hash function.☆37Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆81Updated 6 months ago
- Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations☆69Updated last year
- Test of the USB3 IP Core from Daisho on a Xilinx device☆86Updated 5 years ago
- ☆39Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆54Updated 4 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆133Updated 5 months ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆29Updated 6 years ago
- Bitcoin miner for Xilinx FPGAs☆93Updated 11 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- FuseSoC standard core library☆115Updated last month
- Extensible FPGA control platform☆54Updated last year
- SoC based on VexRiscv and ICE40 UP5K☆151Updated 7 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆84Updated 5 years ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆39Updated 9 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆47Updated 9 years ago
- Bitstream relocation and manipulation tool.☆40Updated last year
- Mathematical Functions in Verilog☆85Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆58Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- Yet Another RISC-V Implementation☆85Updated 2 months ago
- Cryptonight Monero Verilog code for ASIC☆20Updated 6 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago