Render waveforms inside VSCode with WaveDrom
☆40May 25, 2026Updated last month
Alternatives and similar repositories for waveform-render-vscode
Users that are interested in waveform-render-vscode are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definiti…☆34Nov 6, 2024Updated last year
- Loam system models☆16Dec 30, 2019Updated 6 years ago
- SystemVerilog language server client for Visual Studio Code☆23Dec 30, 2022Updated 3 years ago
- [deprecated]use mshr-h/vscode-verilog-hdl-support☆24Nov 3, 2018Updated 7 years ago
- ☆16Jun 23, 2026Updated last month
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 👾 Design ∪ Hardware☆79Jul 1, 2026Updated 3 weeks ago
- ☆21Jan 18, 2024Updated 2 years ago
- GHDL C extensions☆12Feb 20, 2020Updated 6 years ago
- D3.js and ELK based schematic visualizer☆122May 13, 2026Updated 2 months ago
- RISC-V OpenWrt Port☆17Oct 30, 2018Updated 7 years ago
- Projects published on controlpaths.com and hackster.io☆42Jul 18, 2022Updated 4 years ago
- iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.☆11Mar 4, 2023Updated 3 years ago
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 4 years ago
- Web-based HDL diagramming tool☆85May 1, 2023Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- AHB Bus lite v3.0☆17Aug 7, 2019Updated 6 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 5 years ago
- A basic documentation generator for Verilog, similar to Doxygen.☆13Aug 5, 2016Updated 9 years ago
- Program to scan for malicious FPGA designs.☆17Mar 20, 2021Updated 5 years ago
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- SystemVerilog extension for Visual Studio Code☆14Dec 18, 2018Updated 7 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆54Jun 5, 2022Updated 4 years ago
- Visual Studio Code extension that provides fast and easy way to peek other forms of a hexadecimal value.☆17Feb 9, 2023Updated 3 years ago
- An implementation of WaveDrom which outputs TikZ for use in LaTeX documents.☆47Dec 5, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A curated list of awesome resources for HDL design and verification☆175Updated this week
- CBM 1551 paddle replacement / mass storage using an SD card interfacing with the Commodore C16/116/Plus4 simulating a TCBM bus 1551 disk …☆16Jun 18, 2026Updated last month
- Cross EDA Abstraction and Automation☆42Nov 17, 2025Updated 8 months ago
- Python library for operations with VCD and other digital wave files☆55May 19, 2026Updated 2 months ago
- Source code and resources to the 1995 3DO title Star Fighter☆16Apr 25, 2024Updated 2 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆727Dec 14, 2025Updated 7 months ago
- HTML & Js based VCD viewer☆83Feb 16, 2026Updated 5 months ago
- Helper of yaml file generation from single master yaml file.☆10Mar 17, 2020Updated 6 years ago
- Flappy Bird core for MiSTer, MiST, DeMiSTify, Pocket, Xilinx, GoWin, ...☆21Aug 4, 2023Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- HDL symbol generator☆204Feb 2, 2023Updated 3 years ago
- Syntax highlighting for various PCB (Printed Circuit Board) formats.☆21Feb 10, 2022Updated 4 years ago
- Verilog Language Extension for Visual Studio☆20Jul 9, 2026Updated 2 weeks ago
- SystemVerilog language server☆583Updated this week
- ☆15Jul 29, 2023Updated 2 years ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- A Python 3 C++ extension to simplify development using USRP software-defined radios.☆12Mar 16, 2026Updated 4 months ago