dumpo / digital_IC_design_notes
数字IC设计 学习笔记
☆129Updated 3 years ago
Alternatives and similar repositories for digital_IC_design_notes:
Users that are interested in digital_IC_design_notes are comparing it to the libraries listed below
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆83Updated 3 years ago
- 数字IC秋招项目、手撕代码☆34Updated 11 months ago
- ☆143Updated last month
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆199Updated last year
- AMBA bus lecture material☆422Updated 5 years ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆77Updated this week
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆163Updated 5 months ago
- AXI协议规范中文翻译版☆143Updated 2 years ago
- 车牌识别,FPGA,2019全国大学生集成电路创新创业大赛☆137Updated 5 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆119Updated 3 years ago
- FPGA☆123Updated 5 years ago
- CPU Design Based on RISCV ISA☆105Updated 10 months ago
- 【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器☆141Updated 2 years ago
- 2023集创赛紫光同创杯一等奖项目☆107Updated last year
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆14Updated 3 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆32Updated 2 years ago
- 基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现☆318Updated last year
- ARM中通过APB总线连接的UART模块☆64Updated 5 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆144Updated 4 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆167Updated 6 years ago
- upgrade to e203 (a risc-v core)☆41Updated 4 years ago
- Vivado诸多IP,包括图像处理等☆203Updated 8 months ago
- this repository is vim cfg for verilog.☆45Updated 8 months ago
- FPGA实现简单的图像处理算法☆41Updated 2 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- Awesome ASIC design verification☆292Updated 3 years ago
- FPGA project☆217Updated 3 years ago
- Step by step tutorial for building CortexM0 SoC☆36Updated 3 years ago
- The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…☆37Updated 11 months ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆175Updated last year