siyueyinghua / UVMInPracticesByZhangQiang

Related projects ⓘ

Alternatives and complementary repositories for UVMInPracticesByZhangQiang

• emwzq / example_uvm
  UVM实战随书源码
  ☆42Updated 5 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆100Updated 10 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆90Updated 4 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆152Updated 6 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆170Updated 4 years ago
• ForrestBlue / cortexm0ds
  ☆52Updated 8 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆121Updated 5 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆75Updated 2 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆87Updated last year
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆147Updated 4 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆36Updated 2 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆90Updated 3 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆108Updated 2 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆46Updated 3 years ago
• wudayemen / gen_apb_file
  ☆62Updated 3 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆111Updated 3 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆171Updated last year
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆104Updated 6 years ago
• flyskywalker / ahb_sramc
  ahb scram controller, design and verification
  ☆27Updated 6 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆129Updated 6 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆49Updated 4 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆93Updated 6 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆121Updated 5 months ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆83Updated 4 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆118Updated 3 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆54Updated last year
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆130Updated 2 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆45Updated 3 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆72Updated 12 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆67Updated 10 years ago