dumpo / my_verilog_projects
数字IC秋招项目、手撕代码
☆35Updated last year
Alternatives and similar repositories for my_verilog_projects:
Users that are interested in my_verilog_projects are comparing it to the libraries listed below
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆169Updated 6 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆121Updated 3 years ago
- VIP for AXI Protocol☆132Updated 2 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆102Updated 4 months ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆148Updated 5 years ago
- IC Verification & SV Demo☆53Updated 3 years ago
- This is the main repository for all the examples for the book Practical UVM☆190Updated 4 years ago
- UVM examples and projects☆132Updated 6 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆114Updated 7 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆88Updated last year
- uvm AXI BFM(bus functional model)☆244Updated 11 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆84Updated 3 years ago
- ☆19Updated 5 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆60Updated last year
- AXI DMA 32 / 64 bits☆112Updated 10 years ago
- AXI总线连接器☆97Updated 5 years ago
- Radix-4 1024 point fft in verilog☆10Updated 5 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆23Updated 2 years ago
- An uvm verification env for ahb2apb bridge☆50Updated 4 years ago
- UVM AHB VIP☆83Updated 5 months ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆201Updated last year
- ARM中通过APB总线连接的UART模块☆65Updated 5 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆98Updated 7 years ago
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆13Updated 3 years ago
- 数字IC设计 学习笔记☆132Updated 3 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆140Updated 6 years ago
- Reference examples and short projects using UVM Methodology☆264Updated 2 years ago
- Awesome ASIC design verification☆295Updated 3 years ago
- AMBA bus lecture material☆432Updated 5 years ago