Alternatives and similar repositories for The-project-of-Verilog:

Users that are interested in The-project-of-Verilog are comparing it to the libraries listed below

• lucky-wfw / IC_System_Design
  Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …
  ☆26Updated 4 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆54Updated 2 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆116Updated 3 years ago
• gillianGan / ahb_sram_master
  ☆18Updated 4 years ago
• Aperture-Electronic / SystemVerilog-Bitmap-Library-AXI-Image-VIP
  Bitmap Processing Library & AXI-Stream Video Image VIP
  ☆30Updated 2 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆34Updated 10 months ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆94Updated 4 years ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆77Updated 3 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆57Updated last year
• Aashish3970 / MNIST_FPGA
  3 layern artificial ANN to recognize handwritten digits and implement in FPGA
  ☆8Updated 4 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆49Updated 3 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆24Updated 2 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆91Updated 7 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆48Updated 4 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆35Updated 9 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆47Updated 3 years ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆30Updated 3 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆81Updated last year
• Buddhimah / System-Bus-Design-Verilog
  This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
  ☆32Updated 5 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆163Updated 6 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆106Updated 10 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆99Updated last month
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆45Updated 4 years ago
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆41Updated 4 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆41Updated 3 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆80Updated 2 months ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆60Updated 5 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆28Updated 3 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆52Updated 10 years ago