Some design examples of Verilog about digital circuits
☆30Nov 21, 2020Updated 5 years ago
Alternatives and similar repositories for The-project-of-Verilog
Users that are interested in The-project-of-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …☆31Nov 21, 2020Updated 5 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆141May 14, 2021Updated 5 years ago
- SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs☆21Dec 15, 2019Updated 6 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆22Jan 14, 2018Updated 8 years ago
- Connecting FPGA and Arduino using SPI.☆25Apr 30, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- 北京大学数字集成电路设计课程作业—FPGA设计【Assignment of digital integrated circuit design course of Peking University】☆48Jan 1, 2022Updated 4 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆115Dec 15, 2021Updated 4 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Jan 6, 2020Updated 6 years ago
- SPI interface connect to APB BUS with Verilog HDL☆42Jun 27, 2021Updated 4 years ago
- Wishbone to ARM AMBA 4 AXI☆16May 25, 2019Updated 7 years ago
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- 数字IC设计 学习笔记☆168Jan 26, 2022Updated 4 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Jan 13, 2015Updated 11 years ago
- wifi☆12Jun 13, 2017Updated 8 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆21Apr 8, 2025Updated last year
- ☆50Nov 3, 2023Updated 2 years ago
- Verilog Code for I2C Protocol☆19Nov 12, 2020Updated 5 years ago
- A collection of great digital IC project/tutorial/website etc..☆154May 10, 2022Updated 4 years ago
- An uvm verification env for ahb2apb bridge☆58Apr 9, 2021Updated 5 years ago
- Verilog FPGA code : including experimental DSP audio processor☆13Dec 1, 2020Updated 5 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Feb 25, 2019Updated 7 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. …☆15Jan 19, 2018Updated 8 years ago
- ☆13May 28, 2022Updated 3 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆17Jul 7, 2018Updated 7 years ago
- hdmi-ts Project☆13Jun 11, 2017Updated 8 years ago
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆21Feb 16, 2022Updated 4 years ago
- ☆23Feb 10, 2024Updated 2 years ago
- AHB-APB Bridge RTL Design☆16Apr 19, 2018Updated 8 years ago
- UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…☆16Dec 23, 2024Updated last year
- Fully automatic brain tumor segmentation using the Modified 3DUNet architecture for Brats 2020 Challenge.☆16Jun 29, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Try to implement and test CVPR 2019 paper "Res2Net: A New Multi-scale Backbone Architecture" in PyTorch.☆18Jun 7, 2020Updated 5 years ago
- MP3 Player developed on FPGA(DIGILENT NEXYS 4 DDR)☆16Feb 11, 2019Updated 7 years ago
- Generic AXI to APB bridge☆13Jul 17, 2014Updated 11 years ago
- 基于FPGA的PWM电机控制☆24Jun 17, 2020Updated 5 years ago
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆15Jul 19, 2012Updated 13 years ago
- Identifies ASL Hand Gesture for numbers using image processing in verilog☆15May 3, 2012Updated 14 years ago
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19May 28, 2012Updated 13 years ago