Alternatives and similar repositories for Wishbone-to-I2C-bus-controller-IP-Verification

Users that are interested in Wishbone-to-I2C-bus-controller-IP-Verification are comparing it to the libraries listed below

• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆36Updated last year
• laplaceyc / VLSI_Design-Implementation
  This repo is "NTHU VLSI System Design and Implementation" course project.
  ☆13Updated 8 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆154Updated 3 years ago
• basemhesham / Design-and-ASIC-Implementation-of-UART
  This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…
  ☆23Updated last year
• KafCoppelia / uvm-mcdf
  Mirror of william_william/uvm-mcdf on Gitee
  ☆28Updated 2 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆53Updated last year
• Ghonimo / Formal-Verification-of-an-AHB2APB-Bridge
  Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…
  ☆20Updated last year
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆17Updated 4 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆64Updated last year
• abdelazeem201 / ICC2_scripts
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.
  ☆21Updated last year
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆25Updated last month
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆108Updated 9 months ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆51Updated last year
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆155Updated 5 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆129Updated 7 years ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆37Updated 3 years ago
• pengwubj / hw_interview_questions
  A collection of commonly asked RTL design interview questions
  ☆35Updated 8 years ago
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆51Updated 5 years ago
• Ni-ChiTing / IC_contest_cell_based_design
  ☆14Updated 4 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆88Updated 3 years ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated 2 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆87Updated last month
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆64Updated 4 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆128Updated 7 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆37Updated 5 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆26Updated 3 years ago
• Noman-10xe / AXI-DMA-Verification
  Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM
  ☆37Updated 3 months ago
• shubhi704 / APB-Protocol
  ☆49Updated 4 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆146Updated 3 months ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆77Updated 7 years ago