MasterPu2020 / IC-design-general
数字IC设计笔试相关的一些电路代码
☆9Updated last year
Alternatives and similar repositories for IC-design-general:
Users that are interested in IC-design-general are comparing it to the libraries listed below
- 数字IC秋招项目、手撕代码☆34Updated 11 months ago
- 数字IC设计 学习笔记☆129Updated 3 years ago
- 数字IC验证案例(SV and UVM)☆26Updated 3 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆119Updated 3 years ago
- AXI总线连接器☆96Updated 5 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆82Updated 3 years ago
- IC Verification & SV Demo☆52Updated 3 years ago
- fpga跑sobel识别算法☆29Updated 4 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆60Updated 7 months ago
- upgrade to e203 (a risc-v core)☆40Updated 4 years ago
- FFT implement by verilog_测试验证已通过☆54Updated 8 years ago
- this repository is vim cfg for verilog.☆45Updated 7 months ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆32Updated 2 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆50Updated last year
- ☆141Updated last month
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- AXI协议规范中文翻译版☆141Updated 2 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- ☆59Updated 9 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆17Updated last year
- Step by step tutorial for building CortexM0 SoC☆36Updated 2 years ago
- Some design examples of Verilog about digital circuits☆25Updated 4 years ago
- Senior Design Project at UW-Madison ECE☆14Updated last year
- Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …☆27Updated 4 years ago
- ☆19Updated last year
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆166Updated 6 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆21Updated 2 years ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆46Updated last year
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆21Updated 6 years ago