MasterPu2020 / IC-design-general
数字IC设计笔试相关的一些电路代码
☆9Updated last year
Alternatives and similar repositories for IC-design-general:
Users that are interested in IC-design-general are comparing it to the libraries listed below
- fpga跑sobel识别算法☆32Updated 4 years ago
- 数字IC秋招项目、手撕代码☆34Updated last year
- 数字IC验证案例(SV and UVM)☆26Updated 3 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆83Updated 3 years ago
- IC Verification & SV Demo☆52Updated 3 years ago
- Step by step tutorial for building CortexM0 SoC☆37Updated 3 years ago
- AXI总线连接器☆97Updated 5 years ago
- FFT implement by verilog_测试验证已通过☆55Updated 8 years ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆45Updated last year
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆48Updated 8 months ago
- 数字IC设计 学习笔记☆129Updated 3 years ago
- AXI Interconnect☆47Updated 3 years ago
- ☆18Updated 5 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆21Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆61Updated 8 months ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆16Updated 11 months ago
- FPGA图像处理仿真平台☆26Updated 3 years ago
- CPU Design Based on RISCV ISA☆105Updated 10 months ago
- An uvm verification env for ahb2apb bridge☆50Updated 4 years ago
- ☆61Updated 9 years ago
- Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …☆27Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- FPGA实现简单的图像处理算法☆42Updated 2 years ago
- upgrade to e203 (a risc-v core)☆42Updated 4 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆22Updated 2 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- MNIST using tensorflow, c++ and fpga (zynq7010)☆26Updated 2 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 2 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆32Updated 2 years ago