Alternatives and similar repositories for IC-design-general

Users that are interested in IC-design-general are comparing it to the libraries listed below

• dumpo / digital_IC_design_notes
  数字IC设计 学习笔记
  ☆155Updated 3 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆38Updated last year
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆97Updated 3 years ago
• RongyeL / EasyAXI
  ☆69Updated 3 weeks ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆104Updated 5 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆163Updated 3 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆130Updated 4 years ago
• xiesicong / fpga_sobel_ov5640_hdmi
  fpga跑sobel识别算法
  ☆39Updated 4 years ago
• tyxiumud / gvim_for_verilog
  this repository is vim cfg for verilog.
  ☆50Updated last year
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆149Updated 3 weeks ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆59Updated 9 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆121Updated 11 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆180Updated 7 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆54Updated 3 years ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆57Updated last year
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆122Updated last year
• brentwang-lab / uvm_tb_gen
  This is for uvm_tb_gen
  ☆41Updated 7 months ago
• malapatipoojitha / AHB2APB-Bridge
  ☆10Updated 4 years ago
• adki / AMBA_AXI_AHB_APB
  AMBA bus lecture material
  ☆465Updated 5 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆56Updated 4 years ago
• KafCoppelia / uvm-mcdf
  Mirror of william_william/uvm-mcdf on Gitee
  ☆27Updated 2 years ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆20Updated last year
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆222Updated 2 years ago
• hxfycy / 1024-point-fft
  Radix-4 1024 point fft in verilog
  ☆12Updated 5 years ago
• chengquan / IC_FLOW
  ☆17Updated last year
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆67Updated last year
• ForrestBlue / cortexm0ds
  ☆69Updated 9 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆132Updated 6 years ago
• boaaaang / CNN-Implementation-in-Verilog
  Convolutional Neural Network RTL-level Design
  ☆70Updated 3 years ago
• lauchinyuan / Asymmetric_async_FIFO
  asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…
  ☆21Updated last year