MasterPu2020 / IC-design-generalLinks
数字IC设计笔试相关的一些电路代码
☆13Updated 2 years ago
Alternatives and similar repositories for IC-design-general
Users that are interested in IC-design-general are comparing it to the libraries listed below
Sorting:
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆106Updated 4 years ago
- 数字IC设计 学习笔记☆159Updated 3 years ago
- AXI总线连接器☆105Updated 5 years ago
- A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction☆65Updated last year
- This is for uvm_tb_gen☆51Updated 10 months ago
- ☆10Updated 4 years ago
- 数字IC秋招项目、手撕代码☆39Updated last year
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆190Updated 7 years ago
- ☆73Updated 9 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆134Updated 4 years ago
- asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…☆26Updated 2 years ago
- IC Verification & SV Demo☆55Updated 4 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- This is the main repository for all the examples for the book Practical UVM☆212Updated 5 years ago
- this repository is vim cfg for verilog.☆54Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- Mirror of william_william/uvm-mcdf on Gitee☆28Updated 3 years ago
- fpga跑sobel识别算法☆44Updated 4 years ago
- CPU Design Based on RISCV ISA☆127Updated last year
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆235Updated 2 years ago
- AXI协议规范中文翻译版☆171Updated 3 years ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆218Updated 2 months ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆135Updated 8 years ago
- practice configure AHB-Lite bus protocol☆19Updated 6 years ago
- ☆153Updated last month
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆177Updated last year
- Pipeline FFT Implementation in Verilog HDL☆152Updated 6 years ago
- PCIE 5.0 Graduation project (Verification Team)☆97Updated last year
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆211Updated 2 years ago