qninth / awesome-digital-icLinks
A collection of great digital IC project/tutorial/website etc..
☆132Updated 3 years ago
Alternatives and similar repositories for awesome-digital-ic
Users that are interested in awesome-digital-ic are comparing it to the libraries listed below
Sorting:
- Some useful documents of Synopsys☆92Updated 4 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆98Updated 6 years ago
- An AXI4 crossbar implementation in SystemVerilog☆193Updated 3 months ago
- ☆72Updated 9 years ago
- Verilog/SystemVerilog Guide☆75Updated last year
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆139Updated 7 years ago
- AXI协议规范中文翻译版☆165Updated 3 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆140Updated 6 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆113Updated 8 years ago
- AXI总线连接器☆105Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆171Updated last year
- Convolutional accelerator kernel, target ASIC & FPGA☆235Updated 2 years ago
- UVM and System Verilog Manuals☆46Updated 6 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆53Updated 8 years ago
- A verilog implementation for Network-on-Chip☆78Updated 7 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆165Updated last year
- Network on Chip Implementation written in SytemVerilog☆195Updated 3 years ago
- This is a detailed SystemVerilog course☆128Updated 9 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆182Updated last year
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆233Updated 2 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆105Updated 3 years ago
- Collect some IC textbooks for learning.☆173Updated 3 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆193Updated 5 years ago
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- ☆65Updated 3 years ago
- VIP for AXI Protocol☆159Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago