qninth / awesome-digital-icLinks
A collection of great digital IC project/tutorial/website etc..
☆122Updated 3 years ago
Alternatives and similar repositories for awesome-digital-ic
Users that are interested in awesome-digital-ic are comparing it to the libraries listed below
Sorting:
- AXI DMA 32 / 64 bits☆121Updated 11 years ago
- AXI总线连接器☆104Updated 5 years ago
- Some useful documents of Synopsys☆85Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆175Updated 3 weeks ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆108Updated 7 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆67Updated last year
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆222Updated 2 years ago
- AXI协议规范中文翻译版☆163Updated 3 years ago
- Awesome ASIC design verification☆323Updated 3 years ago
- This is the main repository for all the examples for the book Practical UVM☆202Updated 4 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆161Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆151Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆90Updated 6 years ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆226Updated 2 years ago
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆97Updated 3 years ago
- This is a detailed SystemVerilog course☆118Updated 6 months ago
- Novel GUI Based UVM Testbench Template Builder☆143Updated 4 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆27Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆130Updated 4 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆180Updated 7 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- VIP for AXI Protocol☆150Updated 3 years ago
- ☆69Updated 9 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆65Updated 2 years ago
- IC Verification & SV Demo☆54Updated 3 years ago
- Collect some IC textbooks for learning.☆164Updated 3 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- AMBA bus generator including AXI, AHB, and APB☆107Updated 4 years ago