A collection of great digital IC project/tutorial/website etc..
☆174Oct 19, 2026Updated 2 weeks ago
Alternatives and similar repositories for awesome-digital-ic
Users that are interested in awesome-digital-ic are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆134Dec 15, 2021Updated 4 years ago
- 数字IC设计 学习笔记☆185Jan 26, 2022Updated 4 years ago
- A simple implementation about LEGv8 instruction set using Verilog HDL.☆12May 8, 2022Updated 4 years ago
- Some design examples of Verilog about digital circuits☆35Nov 21, 2020Updated 5 years ago
- 北京大学数字集成电路设计课程作业—FPGA设计【Assignment of digital integrated circuit design course of Peking University】☆51Jan 1, 2022Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆34Jun 8, 2022Updated 4 years ago
- IHP Open source SG13G2 Tape Out on May 2025 [Testfield T588]☆15Apr 27, 2026Updated 6 months ago
- 数字IC秋招项目、手撕代码☆46Apr 22, 2024Updated 2 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆22May 7, 2024Updated 2 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆37Jul 17, 2025Updated last year
- A curated list of awesome open source hardware design tools☆92Jun 20, 2025Updated last year
- Verilog code for a low power RFID chip that will communicate with I2C sensors.☆13Apr 18, 2014Updated 12 years ago
- 数字IC相关资料☆1,678Jul 1, 2025Updated last year
- An awesome curated list of languages and tools to program FPGAs☆76Jun 22, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Awesome ASIC design verification☆371Feb 9, 2022Updated 4 years ago
- ☆79Apr 23, 2023Updated 3 years ago
- Must-have verilog systemverilog modules☆2,031Mar 12, 2026Updated 7 months ago
- ☆425Apr 13, 2023Updated 3 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆41Aug 13, 2024Updated 2 years ago
- UVM resource from github, run simulation use YASAsim flow☆34Apr 25, 2020Updated 6 years ago
- ☆11Mar 22, 2022Updated 4 years ago
- RTL and UVM test code of a Multi-NoC system☆12Dec 7, 2021Updated 4 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆42Nov 30, 2022Updated 3 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- IHP Open source SG13G2 Tape Out on April 2025 [Testfield T586]☆23Apr 27, 2026Updated 6 months ago
- The Ultra-Low Power RISC-V Core☆1,979Sep 25, 2026Updated last month
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆21Nov 13, 2024Updated last year
- Open-source, license-free MCP server for RTL waveform debug: reads FST waveforms (VCD/FSDB auto-convert) plus a SystemVerilog netlist, wi…☆272Oct 23, 2026Updated 2 weeks ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆17Jul 7, 2018Updated 8 years ago
- SJTU MST3314 course project (CNN). A binary classification convolutional neural network in Verilog.☆15Mar 8, 2026Updated 7 months ago
- ☆23Nov 23, 2022Updated 3 years ago
- Second life for FPGA boards which can be repurposed to DYI/Hobby projects ..............................................................…☆106Jan 12, 2021Updated 5 years ago
- A collection of resources on FPGA devices and development in general☆401May 25, 2017Updated 9 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆41Jun 2, 2021Updated 5 years ago
- 🐆 A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration for *AdderNet*☆22May 27, 2024Updated 2 years ago
- 关于深度学习算法、框架、编译器、加速器的一些理解☆16Jul 2, 2022Updated 4 years ago
- Single Long Short Term Memory (LSTM) cell : Verilog Implementation☆34May 20, 2020Updated 6 years ago
- 一生一芯CPU/目前做到cache/后续主要考虑ASIC DV☆23Jan 13, 2025Updated last year
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆53Jul 11, 2025Updated last year
- Generic AXI to APB bridge☆13Jul 17, 2014Updated 12 years ago