A lock in amplifier running on the RedPitaya's FPGA
☆17Jan 29, 2019Updated 7 years ago
Alternatives and similar repositories for RedPitaya_LockInAmplifier
Users that are interested in RedPitaya_LockInAmplifier are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 使用DDS芯片AD9914产生线性扫频信号☆12Dec 9, 2020Updated 5 years ago
- Simple projects for the RedPitaya board that illustrate the use of standard IPs from Vivado in combination with modules written in Verilo…☆17Aug 4, 2025Updated 7 months ago
- Digital Phase-locked-loop software for Locking a Frequency Comb using a Red Pitaya☆50Dec 4, 2025Updated 3 months ago
- STEP FPGA Development Board - Lattice MachXO2 FPGA☆15Jun 26, 2019Updated 6 years ago
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆32Aug 31, 2020Updated 5 years ago
- Tiny MATLAB-to-C converter (TMC Compiler)☆13Oct 26, 2020Updated 5 years ago
- ☆13May 28, 2021Updated 4 years ago
- Gowin USB3.0 Device Controller IP☆15Aug 20, 2024Updated last year
- GPIB to USB converter☆11Jan 3, 2014Updated 12 years ago
- 高中物理资料☆12Jan 13, 2020Updated 6 years ago
- Thesis: Custom Filter Designs on the Red Pitaya☆12Jan 8, 2018Updated 8 years ago
- Collection of virtual quantum devices☆15Feb 3, 2026Updated last month
- Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.☆16Apr 1, 2018Updated 7 years ago
- VISA header conversion and VISA session component for Lazarus☆10Sep 21, 2014Updated 11 years ago
- FPGA implementation of SKLearn Random Forest☆10Dec 12, 2016Updated 9 years ago
- JPEG Compression using DCT (Discrete Cosine Transform) and DWT (Discrete Wavelet Transform) in Matlab.☆10Nov 26, 2019Updated 6 years ago
- 基于FPGA实验板的多功能数字时钟。利用Quartus实现设计与仿真☆15May 23, 2023Updated 2 years ago
- A CORDIC implementation of square root Verilog calculation on Quartus Prime 16.0, with ability to simulate on ModelSim as well.☆19Jul 24, 2021Updated 4 years ago
- Slicer modules for running subprocesses to operate on data in parallel☆12Feb 23, 2024Updated 2 years ago
- 保研/求职latex简历模版☆21Mar 23, 2025Updated last year
- This is a project for the proposed Homeostasis-based ANN-to-SNN conversion for Inception and Residual architecture.☆10Nov 7, 2018Updated 7 years ago
- Generic slave implementation of the 1-wire protocol in C☆13Mar 3, 2019Updated 7 years ago
- The Berry language for STM32F103.☆11May 14, 2019Updated 6 years ago
- Julia中文社区报告：罗秀哲的开源工具箱☆12Dec 6, 2022Updated 3 years ago
- A highly parallelized implementation of non-maximum suppression for object detection used for self-driving cars.☆14Jan 7, 2017Updated 9 years ago
- Spectroscopy lock application using RedPitaya☆113Mar 16, 2026Updated last week
- IC设计中的一些经典书籍☆13Jul 28, 2020Updated 5 years ago
- a programming game for Python based on Robocode and Turtle.py☆12Jan 24, 2019Updated 7 years ago
- Decision Trees Inference☆14Apr 25, 2018Updated 7 years ago
- ☆17Updated this week
- MATLAB Image Processing Toolkit with 30+ features: transforms, filtering, edge detection, enhancement + a real-time user-friendly visuali…☆14Sep 30, 2025Updated 5 months ago
- Define and generate waveforms to output with your favorite DAC☆12Jan 2, 2019Updated 7 years ago
- Julia package to extend the conversion of Julia arrays to NumPy arrays☆15Jul 12, 2021Updated 4 years ago
- Code and models of the paper "FPGA accelerator for Gradient Boosting Decision Trees".☆15Feb 4, 2021Updated 5 years ago
- 数字IC设计笔试相关的一些电路代码☆15Sep 22, 2023Updated 2 years ago
- COCO Semantic Segmentation Using UNET☆13Jul 7, 2019Updated 6 years ago
- This project is basically ultrasound Beamformer prototype and FPGA is used to control all the modules of the Hardware.☆15Nov 9, 2017Updated 8 years ago
- A DAS-based focused ultrasonic beam synthesis algorithm source code☆17Jun 2, 2025Updated 9 months ago
- Verilog Sigmoid and Tanh functions which can be configured and added to your neural network project☆16Mar 9, 2020Updated 6 years ago