YutingJiang / Digital_IC_Backend_Interview

Related projects ⓘ

Alternatives and complementary repositories for Digital_IC_Backend_Interview

• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆36Updated 5 years ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆67Updated 2 years ago
• sumanth-kalluri / cnn_hardware_acclerator_for_fpga
  This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…
  ☆160Updated 8 months ago
• padhi499 / Image-Classification-using-CNN-on-FPGA
  Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
  ☆121Updated 3 years ago
• dumpo / my_verilog_projects
  数字IC秋招项目、手撕代码
  ☆33Updated 7 months ago
• dumpo / digital_IC_design_notes
  数字IC设计 学习笔记
  ☆119Updated 2 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆127Updated 5 months ago
• BIGWJZ / VLSI-DSP-Review
  ☆54Updated 4 years ago
• mayshin10 / CNN-Accelerator
  Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.
  ☆20Updated 3 years ago
• Giftwen / DC_script
  syn script for DC Compiler
  ☆12Updated 2 years ago
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆187Updated 7 years ago
• zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
  FPGA/AES/LeNet/VGG16
  ☆88Updated 6 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆68Updated 2 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆54Updated 3 months ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆71Updated 5 years ago
• ChunxuGuo / SummerSchool2022
  ☆57Updated 2 years ago
• zlijingtao / Digital-Calibration-of-SAR-ADC
  Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)
  ☆46Updated 6 years ago
• pareddy113 / Design-of-various-multiplier-Array-Booth-Wallace-
  ☆19Updated 10 months ago
• boaaaang / CNN-Implementation-in-Verilog
  Convolutional Neural Network RTL-level Design
  ☆34Updated 3 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆49Updated 3 years ago
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆83Updated 4 years ago
• programer-guan / digital_ic_verification
  数字IC验证案例（SV and UVM）
  ☆25Updated 3 years ago
• AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm
  This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…
  ☆44Updated last year
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆45Updated 4 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆12Updated 3 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆45Updated 3 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆52Updated 8 years ago
• CustomizableComputingLab / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆15Updated 6 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆91Updated 4 years ago
• chengquan / IC_FLOW
  ☆12Updated 10 months ago