数字IC验证案例(SV and UVM)
☆27Apr 27, 2021Updated 4 years ago
Alternatives and similar repositories for digital_ic_verification
Users that are interested in digital_ic_verification are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 数字IC秋招项目、手撕代码☆42Apr 22, 2024Updated last year
- wifi☆12Jun 13, 2017Updated 8 years ago
- UVM resource from github, run simulation use YASAsim flow☆33Apr 25, 2020Updated 5 years ago
- 关于数字IC的笔试面试题☆14Nov 17, 2019Updated 6 years ago
- 为了学习UVM验证相关知识,需要动手尝试实际的项目。作为一个初学者,难以接触到实际的项目,于是我从夏宇闻老师的《Verilog数字系统设计教程》一书中,挑选出一个简单的小设计,作为我的验证对象,并围绕它编写了UVM验证环境。☆24Oct 9, 2020Updated 5 years ago
- IC Verification & SV Demo☆58Sep 29, 2021Updated 4 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆48Jun 19, 2020Updated 5 years ago
- ahb scram controller, design and verification☆28Jun 20, 2018Updated 7 years ago
- An uvm verification env for ahb2apb bridge☆57Apr 9, 2021Updated 4 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Mar 8, 2026Updated 2 weeks ago
- Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org)☆11Apr 9, 2015Updated 10 years ago
- ☆20Aug 22, 2022Updated 3 years ago
- Pointer Networks Implementation to solve Convex-Hull and TSP problems using supervised and RL training.☆15Sep 30, 2023Updated 2 years ago
- Optimal Action Space Search (OASS) is an algorithm for path planning problems on directed acyclic graphs (DAG) based on reinforcement lea…☆12Aug 30, 2023Updated 2 years ago
- ☆19Aug 11, 2022Updated 3 years ago
- SystemVerilog examples and projects☆20Jun 10, 2025Updated 9 months ago
- A transaction level model of a PCI express root complex implemented in systemc☆23Jun 16, 2014Updated 11 years ago
- DDR3 function verification environment in UVM☆26Apr 1, 2018Updated 7 years ago
- 数字IC设计笔试相关的一些电路代码☆15Sep 22, 2023Updated 2 years ago
- c++ version of ViT☆12Nov 13, 2022Updated 3 years ago
- ☆10Jun 4, 2024Updated last year
- Canny Edge detector algorith optimized on the Programmable Logic (HW) of the Zynq-7000 FPGA Architecture☆12Jun 3, 2020Updated 5 years ago
- Official implementation of the ICLR'25 paper "QERA: an Analytical Framework for Quantization Error Reconstruction".☆13Feb 4, 2025Updated last year
- Semiconductor Tester Stuff -- Especially 93k, 93000 -- HP, Agilent, Verigy, Advantest☆19Oct 5, 2013Updated 12 years ago
- Using Xilinx tools, the Unet architecture will be implemented and optimized for FPGA use. Some convolution-transposed conv sub-parts of t…☆17Feb 25, 2021Updated 5 years ago
- ☆14Jun 22, 2022Updated 3 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆116Nov 27, 2017Updated 8 years ago
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…☆18Aug 21, 2018Updated 7 years ago
- 5 stage pipeline, single cycle risc-V implementation☆30Mar 9, 2024Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆24Feb 16, 2022Updated 4 years ago
- 本项目是利用Faster-RCNN算法对目标进行识别与分类。深度学习框架是MXNet,迁移训练和fine-tuning的模型是VGG16和ResNet-101两个模型。语言是python和pyqt。用pyqt简单的做了一个操作界面。界面如图show.png所示☆12Dec 22, 2019Updated 6 years ago
- nuedc.org☆55Sep 7, 2025Updated 6 months ago
- 基于交叉结构光视觉传感器的智能焊缝识别系统☆16Aug 26, 2023Updated 2 years ago
- verilog实现systolic array及配套IO☆12Dec 2, 2024Updated last year
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource…☆61Feb 28, 2026Updated 3 weeks ago
- 基于FPGA的CNN图像分类系统☆15Nov 27, 2021Updated 4 years ago
- ☆19Mar 21, 2023Updated 3 years ago
- Implementation network trimming using pytorch☆15Apr 20, 2020Updated 5 years ago
- Matlab Simulation files for Ultrasonic Phased Arrays☆25Jul 3, 2017Updated 8 years ago