Alternatives and similar repositories for digital_ic_verification

Users that are interested in digital_ic_verification are comparing it to the libraries listed below

• wbbbbbb123 / UVM-based-AHB-bus-SRAM-controller-design-verification-platform-design
  ☆16Updated 3 years ago
• wbbbbbb123 / Sram-controller-design-based-on-AHB-bus
  ☆20Updated 3 years ago
• designsolver / ahb2apb_bridge_vip
  AHB to APB Bridge VIP
  ☆29Updated 6 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆24Updated 5 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆30Updated 5 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆56Updated 4 years ago
• praveenkhemalapure / DDR3-controller-verification
  DDR3 function verification environment in UVM
  ☆25Updated 7 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆35Updated 2 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆53Updated 4 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆41Updated 3 years ago
• feifan1996 / RiscSoC
  RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核
  ☆11Updated 3 years ago
• xdesigns / 4way-cache
  Verilog cache implementation of 4-way FIFO 16k Cache
  ☆20Updated 12 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• MushroomZQ / RISC_VERIF_DEMO_0
  a very simple risc_cpu verification demo with uvm
  ☆26Updated 6 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆54Updated 4 years ago
• DexWen / LMS-Adaptive-filter
  LMS-Adaptive Filter implement using verilog and Matlab
  ☆47Updated 8 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆22Updated 6 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆49Updated 5 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆49Updated 4 years ago
• yvnr4you / SDRAM-Verification
  This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …
  ☆28Updated 8 years ago
• muneebullashariff / spi_vip
  Verification IP for SPI protocol
  ☆20Updated 5 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆70Updated 4 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆37Updated 10 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆37Updated 4 years ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆68Updated 5 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆59Updated 9 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆38Updated 8 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆45Updated 5 years ago
• muneebullashariff / apb_vip
  Verification IP for APB protocol
  ☆29Updated 5 years ago
• markos-stefanidis / FPGA-Based-HDR-algorithm
  Hardware implementation of HDR image producing algorithm
  ☆16Updated 3 years ago