Alternatives and similar repositories for digital_ic_verification

Users that are interested in digital_ic_verification are comparing it to the libraries listed below

• wbbbbbb123 / UVM-based-AHB-bus-SRAM-controller-design-verification-platform-design
  ☆15Updated 2 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆54Updated 4 years ago
• designsolver / ahb2apb_bridge_vip
  AHB to APB Bridge VIP
  ☆29Updated 6 years ago
• feifan1996 / RiscSoC
  RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核
  ☆11Updated 3 years ago
• wbbbbbb123 / Sram-controller-design-based-on-AHB-bus
  ☆20Updated 2 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆54Updated 3 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆27Updated 5 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆44Updated 5 years ago
• Starrynightzyq / ZYNQ-PYNQ-Z2-Gobang
  2018第二届全国大学生FPGA创新设计邀请赛的作品
  ☆60Updated 6 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆101Updated 7 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆50Updated 3 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆127Updated 4 years ago
• muneeb-mbytes / uvm_tb_arch_doc_py
  A python project to automatically generate the UVM testbench document.
  ☆20Updated last year
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆42Updated 3 years ago
• praveenkhemalapure / DDR3-controller-verification
  DDR3 function verification environment in UVM
  ☆25Updated 7 years ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆93Updated 3 years ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆67Updated 5 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆22Updated 6 years ago
• jessepalomera / 10G_EthernetMAC_SystemVerilog_OOP
  Final Project for my course in Advanced Verification with SystemVerilog OOP
  ☆21Updated 3 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆34Updated 4 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆86Updated 7 months ago
• markos-stefanidis / FPGA-Based-HDR-algorithm
  Hardware implementation of HDR image producing algorithm
  ☆16Updated 2 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆24Updated 5 years ago
• alireza-shirzad / Cordic_tanh
  Verilog and matlab implementation of tanh using Cordic algorithm
  ☆11Updated 5 years ago
• flyskywalker / ahb_sramc
  ahb scram controller, design and verification
  ☆27Updated 7 years ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆74Updated 4 years ago
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆48Updated 5 years ago
• MushroomZQ / RISC_VERIF_DEMO_0
  a very simple risc_cpu verification demo with uvm
  ☆24Updated 6 years ago
• xdesigns / 4way-cache
  Verilog cache implementation of 4-way FIFO 16k Cache
  ☆20Updated 12 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆66Updated 4 years ago