programer-guan / digital_ic_verificationLinks
数字IC验证案例（SV and UVM）
☆26Updated 4 years ago
Alternatives and similar repositories for digital_ic_verification
Users that are interested in digital_ic_verification are comparing it to the libraries listed below
Sorting:
- An uvm verification env for ahb2apb bridge☆53Updated 4 years ago
- IC Verification & SV Demo☆54Updated 3 years ago
- 数字IC秋招项目、手撕代码☆35Updated last year
- AHB to APB Bridge VIP☆29Updated 6 years ago
- ahb scram controller, design and verification☆27Updated 6 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆60Updated last year
- ☆14Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆126Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆32Updated 2 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆100Updated 7 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 5 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆23Updated 2 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆90Updated last year
- Simple AMBA VIP, Include axi/ahb/apb☆24Updated 11 months ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆119Updated 7 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- ☆19Updated 2 years ago
- ARM中通过APB总线连接的UART模块☆67Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆39Updated 4 years ago
- UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…☆12Updated 5 months ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- a very simple risc_cpu verification demo with uvm☆23Updated 6 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆48Updated 4 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆172Updated 6 years ago
- UVM AHB VIP☆85Updated 6 months ago
- RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核☆10Updated 3 years ago
- ☆40Updated last year
- UVM Verification IP to uart2bus IP.☆22Updated 3 years ago