mahmutefil / AXI2APB-Bridge-Design-and-VerificationLinks
In this repository, the RTL design and verification of the axi2apb bridge communication protocol are realized. In this system, the preferred AXI bus will be axi4-lite and the APB bus will be APB3. You can find the more detailed information about the bridge protocol by looking at the AXI to APB Bridge LogiCORE IP Product Guide.
☆16Updated 3 years ago
Alternatives and similar repositories for AXI2APB-Bridge-Design-and-Verification
Users that are interested in AXI2APB-Bridge-Design-and-Verification are comparing it to the libraries listed below
Sorting:
- AXI Interconnect☆51Updated 3 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆23Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- ☆20Updated 2 years ago
- ☆26Updated 4 years ago
- Verification IP for APB protocol☆68Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆34Updated 2 years ago
- General Purpose AXI Direct Memory Access☆57Updated last year
- DOULOS Easier UVM Code Generator☆34Updated 8 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 6 months ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆25Updated 8 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆44Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- ☆36Updated 9 years ago
- This is the repository for the IEEE version of the book☆68Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆69Updated 5 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆21Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆68Updated 4 years ago
- AMBA 3 AHB UVM TB☆32Updated 6 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆33Updated 5 years ago
- Implementation of the PCIe physical layer☆47Updated 3 weeks ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆60Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 2 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago