zli87 / Integrated_Circuit_Design_Laboratory_IC_Lab
Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.
☆19Updated 3 years ago
Alternatives and similar repositories for Integrated_Circuit_Design_Laboratory_IC_Lab:
Users that are interested in Integrated_Circuit_Design_Laboratory_IC_Lab are comparing it to the libraries listed below
- SystemVerilog modules and classes commonly used for verification☆45Updated last week
- SoC Based on ARM Cortex-M3☆25Updated this week
- Synopsys Design compiler, VCS and Tetra-MAX☆17Updated 6 years ago
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 6 years ago
- Logic synthesis and ABC based optimization☆48Updated last month
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- General Purpose AXI Direct Memory Access☆48Updated 8 months ago
- AXI X-Bar☆19Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆33Updated 2 years ago
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- Simple single-port AXI memory interface☆37Updated 7 months ago
- ☆18Updated 4 years ago
- Connecting SystemC with SystemVerilog☆37Updated 12 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆19Updated 10 months ago
- System on Chip verified with UVM/OSVVM/FV☆23Updated 3 weeks ago
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆14Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆18Updated 7 years ago
- sram/rram/mram.. compiler☆30Updated last year
- The memory model was leveraged from micron.☆22Updated 6 years ago
- Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library☆30Updated 3 years ago
- my UVM training projects☆29Updated 5 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆21Updated 2 years ago
- UVM resource from github, run simulation use YASAsim flow☆26Updated 4 years ago
- Build an open source, extremely simple DMA.☆19Updated 5 years ago
- Useful UVM extensions☆21Updated 6 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- This is the repository for the IEEE version of the book☆53Updated 4 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆44Updated last week