zli87 / Integrated_Circuit_Design_Laboratory_IC_LabLinks
Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.
☆23Updated 3 years ago
Alternatives and similar repositories for Integrated_Circuit_Design_Laboratory_IC_Lab
Users that are interested in Integrated_Circuit_Design_Laboratory_IC_Lab are comparing it to the libraries listed below
Sorting:
- General Purpose AXI Direct Memory Access☆53Updated last year
- my UVM training projects☆34Updated 6 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 7 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆18Updated 7 years ago
- SoC Based on ARM Cortex-M3☆32Updated 2 months ago
- Generic FIFO implementation with optional FWFT☆59Updated 5 years ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆80Updated 8 months ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 6 months ago
- IC implementation of TPU☆127Updated 5 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆106Updated 4 years ago
- System on Chip verified with UVM/OSVVM/FV☆29Updated last month
- Logic synthesis and ABC based optimization☆49Updated last week
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆64Updated 8 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆32Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- SystemVerilog RTL Linter for YoSys☆21Updated 7 months ago
- This is a verilog implementation of 4x4 systolic array multiplier☆57Updated 4 years ago
- This is the repository for the IEEE version of the book☆66Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆40Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆29Updated last month
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆29Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆34Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- Connecting SystemC with SystemVerilog☆41Updated 13 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆180Updated 5 years ago
- UVM and System Verilog Manuals☆43Updated 6 years ago