zli87 / Integrated_Circuit_Design_Laboratory_IC_Lab
Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.
☆23Updated 3 years ago
Alternatives and similar repositories for Integrated_Circuit_Design_Laboratory_IC_Lab:
Users that are interested in Integrated_Circuit_Design_Laboratory_IC_Lab are comparing it to the libraries listed below
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 6 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- ☆11Updated 3 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆49Updated 7 years ago
- Build an open source, extremely simple DMA.☆21Updated 6 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆49Updated 4 years ago
- Logic synthesis and ABC based optimization☆49Updated 2 weeks ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆23Updated last year
- sram/rram/mram.. compiler☆32Updated last year
- Implementing Different Adder Structures in Verilog☆64Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆13Updated 4 years ago
- IC implementation of TPU☆113Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- tpu-systolic-array-weight-stationary☆23Updated 3 years ago
- Verilog Implementation of 32-bit Floating Point Adder☆39Updated 4 years ago
- ☆31Updated 5 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆17Updated 6 years ago
- This is a tutorial on standard digital design flow☆75Updated 3 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆12Updated 8 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆22Updated 5 years ago
- MAC system with IEEE754 compatibility☆11Updated last year
- ☆26Updated 5 years ago
- Asynchronous fifo in verilog☆33Updated 9 years ago
- This is the repository for the IEEE version of the book☆57Updated 4 years ago
- Template for project1 TPU☆18Updated 3 years ago
- SystemVerilog examples and projects☆17Updated 6 years ago
- DMA Hardware Description with Verilog☆13Updated 5 years ago