Alternatives and similar repositories for Integrated_Circuit_Design_Laboratory_IC_Lab:

Users that are interested in Integrated_Circuit_Design_Laboratory_IC_Lab are comparing it to the libraries listed below

• max2468tw / IC_Lab
  NCTU 2018 Spring Integrated Circuit Design Laboratory
  ☆24Updated 6 years ago
• UNSAMDCI / PDK_ONC5
  Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library
  ☆31Updated 3 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆55Updated 4 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆17Updated 6 years ago
• Ni-ChiTing / IC_contest_cell_based_design
  ☆11Updated 3 years ago
• pulp-platform / axi_node
  AXI X-Bar
  ☆19Updated 4 years ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆50Updated 7 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆45Updated last month
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆36Updated 2 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆27Updated 3 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆22Updated 11 months ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆32Updated 8 years ago
• yutongshen / RISC-V_SoC
  ☆35Updated last year
• amamory-verification / uvm-basics
  my UVM training projects
  ☆30Updated 5 years ago
• laplaceyc / VLSI_Design-Implementation
  This repo is "NTHU VLSI System Design and Implementation" course project.
  ☆13Updated 7 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 9 months ago
• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆15Updated 3 years ago
• AkeelMedina22 / RISC-V-Pipelined-Processor
  A Verilog based 5-stage fully functional pipelined RISC-V Processor code.
  ☆26Updated 3 years ago
• tianrenz2 / Single-Cycle-Processor
  Single-Cycle RISC-V Processor in systemverylog
  ☆20Updated 5 years ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 6 years ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆37Updated 8 months ago
• PacoReinaCampo / SoC-DV
  System on Chip verified with UVM/OSVVM/FV
  ☆23Updated last month
• Nikola2444 / RISC-V-vector-processor
  ☆12Updated 2 years ago
• AmrElsersy / DMA
  DMA Hardware Description with Verilog
  ☆12Updated 5 years ago
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆19Updated 2 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆51Updated this week
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆20Updated 5 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago
• pansygrass / ecc
  Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…
  ☆42Updated 9 years ago