zli87 / Integrated_Circuit_Design_Laboratory_IC_LabLinks
Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.
☆24Updated 4 years ago
Alternatives and similar repositories for Integrated_Circuit_Design_Laboratory_IC_Lab
Users that are interested in Integrated_Circuit_Design_Laboratory_IC_Lab are comparing it to the libraries listed below
Sorting:
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 3 weeks ago
- AHB DMA 32 / 64 bits☆57Updated 11 years ago
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 7 years ago
- This is a tutorial on standard digital design flow☆82Updated 4 years ago
- ☆40Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- SystemVerilog modules and classes commonly used for verification☆54Updated last month
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆65Updated 2 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆73Updated 6 years ago
- The memory model was leveraged from micron.☆25Updated 7 years ago
- ☆67Updated 3 years ago
- my UVM training projects☆38Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library☆36Updated 3 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆54Updated 8 years ago
- This is the repository for the IEEE version of the book☆77Updated 5 years ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆33Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆114Updated 5 years ago
- AMBA 3 AHB UVM TB☆34Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆74Updated 6 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- SoC Based on ARM Cortex-M3☆36Updated 7 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- A verilog implementation for Network-on-Chip☆79Updated 7 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago