Daniel-GGB / My-Digital-IC-LibraryLinks
我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
☆90Updated 3 years ago
Alternatives and similar repositories for My-Digital-IC-Library
Users that are interested in My-Digital-IC-Library are comparing it to the libraries listed below
Sorting:
- 数字IC设计 学习笔记☆138Updated 3 years ago
- 数字IC秋招项目、手撕代码☆35Updated last year
- AXI总线连接器☆99Updated 5 years ago
- ARM中通过APB总线连接的UART模块☆67Updated 5 years ago
- ☆146Updated this week
- AXI协议规范中文翻译版☆152Updated 2 years ago
- CPU Design Based on RISCV ISA☆113Updated last year
- 2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆180Updated 7 months ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆172Updated 6 years ago
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆95Updated 2 weeks ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆127Updated 4 years ago
- IC Verification & SV Demo☆54Updated 3 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- AXI DMA 32 / 64 bits☆113Updated 10 years ago
- this repository is vim cfg for verilog.☆48Updated 10 months ago
- ☆65Updated 9 years ago
- Some useful documents of Synopsys☆75Updated 3 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆207Updated last year
- This is for uvm_tb_gen☆26Updated 4 months ago
- ☆44Updated last month
- ☆39Updated 4 years ago
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆14Updated 3 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆63Updated 6 years ago
- ☆19Updated 5 years ago
- some interesting demos for starters☆81Updated 2 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆23Updated 2 years ago
- Radix-4 1024 point fft in verilog☆10Updated 5 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆40Updated 2 years ago
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆19Updated last year
- verilog实现TPU中的脉动阵列计算卷积的module☆118Updated last month