Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It also includes various common circuits, such as FIFO, RAM, state machine, and so on. All designs have been validated by Testbench and FPGA functions.
☆32Nov 21, 2020Updated 5 years ago
Alternatives and similar repositories for IC_System_Design
Users that are interested in IC_System_Design are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 6 years ago
- A digital phase-locked loop implemented on Spartan-6☆14Jul 10, 2018Updated 8 years ago
- Implement Phase Modulation Radio Transmitter in FPGA Altera MAX10, with Marsohod3bis FPGA board.☆14May 4, 2017Updated 9 years ago
- There are the documents, floating and fixed-point algorithms, and Verilog codes for the project.☆11Jun 27, 2016Updated 10 years ago
- Some design examples of Verilog about digital circuits☆35Nov 21, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆13Aug 12, 2020Updated 6 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆36Jul 4, 2024Updated 2 years ago
- ❤️ This is a Xilinx_FPGA _Spartan6 project for modulation 2ASK QPSK ADC DAC ROM SCI☆18Mar 28, 2018Updated 8 years ago
- Mirror of the now discontinued ORCA RISC-V processor from VectorBlox.☆11Feb 11, 2020Updated 6 years ago
- 32位单精度浮点数加法器和除法器是用于执行符合IEEE 754标准的浮点数加法、除法运算的数字电路。这样的电路设计在现代计算机系统中扮演着重要角色,特别是在处理需要高精度计算的任务时。这个小项目实现了一个符合IEEE 754 单精度浮点数标准(32 位)的浮点数加法器与除法…☆15Aug 14, 2025Updated last year
- this repository is a project about iic master, created by gyj in second half of 2017☆18Jun 30, 2018Updated 8 years ago
- FPGA-based Fully Digital FM Transmitter using SDR (Software-Defined Radio) techniquies as up-converter using hpsdm, comb filters, cordic …☆18Mar 15, 2021Updated 5 years ago
- Documentation for the tinyNX33U SoM and related boards☆13Oct 8, 2026Updated 3 weeks ago
- OscillatorIMP ecosystem FPGA IP sources☆28Feb 22, 2026Updated 8 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆150May 14, 2021Updated 5 years ago
- UART verification using UVM with functional coverage, scoreboard, and test scenarios, simulated on QuestaSim.☆15Feb 26, 2025Updated last year
- 2021 年新版臺大電機系預選網站 (https://course.ntuee.org/)☆16Dec 31, 2024Updated last year
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆10Feb 27, 2023Updated 3 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 8 years ago
- ☆11Mar 22, 2022Updated 4 years ago
- Hardware Architecture for 30fps Full-HD Guided Image Filter☆12Jul 20, 2019Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- FPGA纯逻辑实现modbus通信☆27Sep 5, 2022Updated 4 years ago
- Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware☆13Aug 24, 2020Updated 6 years ago
- ☆10Dec 12, 2020Updated 5 years ago
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆15Aug 21, 2023Updated 3 years ago
- FPGA based FM radio with traditional IF architecture and digital IQ demodulation☆25Oct 1, 2024Updated 2 years ago
- ☆26Aug 10, 2023Updated 3 years ago
- O'Reilly Course, In-Memory Computing Essentials☆10Oct 16, 2020Updated 6 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆92Nov 26, 2021Updated 4 years ago
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆16Jun 28, 2021Updated 5 years ago
- Simple RiscV core for academic purpose.☆22Apr 29, 2020Updated 6 years ago
- 一款Cyclone Ⅳ(EP4CE6E22C8N)的FPGA板,板载JTAG下载电路、HDMI(output)、UART、SDRAM、TFT-LCD等☆20Jun 29, 2023Updated 3 years ago
- 4通道CMOS相机上位机项目描述:硬件FPGA进行CMOS图像采集,通过网络传输数据,然后在PC上实现4通道CMOS图像显示;上位机可以通过界面操作完成对相机的控制。☆29Jul 21, 2018Updated 8 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- This place provide different SRAM cells netlist to be simulated with HSpice tool in sub-20nm FinFET technologies.☆12Dec 31, 2020Updated 5 years ago
- EdgeAI Electronics☆12Updated this week