lucky-wfw / IC_System_DesignLinks
Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It also includes various common circuits, such as FIFO, RAM, state machine, and so on. All designs have been validated by Testbench and FPGA functions.
☆29Updated 4 years ago
Alternatives and similar repositories for IC_System_Design
Users that are interested in IC_System_Design are comparing it to the libraries listed below
Sorting:
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆48Updated 6 years ago
- AXI DMA 32 / 64 bits☆121Updated 11 years ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- ARM中通过APB总线连接的UART模块☆68Updated 5 years ago
- ☆69Updated 9 years ago
- AXI总线连接器☆105Updated 5 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆132Updated 4 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆67Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆69Updated last year
- SPI interface connect to APB BUS with Verilog HDL☆37Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆85Updated last year
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆62Updated 3 years ago
- ☆38Updated 10 years ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- 3×3脉动阵列乘法器☆46Updated 6 years ago
- AMBA bus generator including AXI, AHB, and APB☆107Updated 4 years ago
- 我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆101Updated 3 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆109Updated 7 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- APB to I2C☆43Updated 11 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆224Updated 2 years ago
- Pipeline FFT Implementation in Verilog HDL☆137Updated 6 years ago
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆208Updated 2 years ago
- 基于FPGA的三速以太网UDP协议栈设计☆32Updated last year
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated last year
- Cortex M0 based SoC☆75Updated 4 years ago