lucky-wfw / IC_System_DesignLinks
Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It also includes various common circuits, such as FIFO, RAM, state machine, and so on. All designs have been validated by Testbench and FPGA functions.
☆28Updated 4 years ago
Alternatives and similar repositories for IC_System_Design
Users that are interested in IC_System_Design are comparing it to the libraries listed below
Sorting:
- ARM中通过APB总线连接的UART模块☆67Updated 5 years ago
- ☆67Updated 9 years ago
- SPI interface connect to APB BUS with Verilog HDL☆34Updated 4 years ago
- AXI DMA 32 / 64 bits☆115Updated 11 years ago
- AXI总线连接器☆100Updated 5 years ago
- Pipeline FFT Implementation in Verilog HDL☆122Updated 6 years ago
- FFT implement by verilog_测试验证已通过☆58Updated 8 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆65Updated 11 months ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆62Updated 2 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆49Updated 6 years ago
- 基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）☆48Updated 5 years ago
- ☆36Updated 9 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆127Updated 4 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆101Updated 7 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- AXI Interconnect☆50Updated 3 years ago
- 基于FPGA的三速以太网UDP协议栈设计☆27Updated last year
- Bitmap Processing Library & AXI-Stream Video Image VIP☆33Updated 3 years ago
- IC Verification & SV Demo☆54Updated 3 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆63Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- Cortex M0 based SoC☆73Updated 3 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- APB to I2C☆42Updated 11 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago