Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It also includes various common circuits, such as FIFO, RAM, state machine, and so on. All designs have been validated by Testbench and FPGA functions.
☆32Nov 21, 2020Updated 5 years ago
Alternatives and similar repositories for IC_System_Design
Users that are interested in IC_System_Design are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆19Mar 6, 2020Updated 6 years ago
- There are the documents, floating and fixed-point algorithms, and Verilog codes for the project.☆11Jun 27, 2016Updated 10 years ago
- Some design examples of Verilog about digital circuits☆32Nov 21, 2020Updated 5 years ago
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆14Aug 12, 2020Updated 6 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆35Jul 4, 2024Updated 2 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆148May 14, 2021Updated 5 years ago
- FPGA-based Fully Digital FM Transmitter using SDR (Software-Defined Radio) techniquies as up-converter using hpsdm, comb filters, cordic …☆18Mar 15, 2021Updated 5 years ago
- 32位单精度浮点数加法器和除法器是用于执行符合IEEE 754标准的浮点数加法、除法运算的数字电路。这样的电路设计在现代计算机系统中扮演着重要角色，特别是在处理需要高精度计算的任务时。这个小项目实现了一个符合IEEE 754 单精度浮点数标准（32 位）的浮点数加法器与除法…☆15Aug 14, 2025Updated last year
- This document is a project of cmos image sensor system. The doc mainly includes LUPA4000 Cmos sensor driving, SDRAM storage, LVDS data re…☆12Feb 7, 2021Updated 5 years ago
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- 2021 年新版臺大電機系預選網站 (https://course.ntuee.org/)☆16Dec 31, 2024Updated last year
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 6 years ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Mar 5, 2018Updated 8 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆10Feb 27, 2023Updated 3 years ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆17Feb 29, 2024Updated 2 years ago
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆90Nov 26, 2021Updated 4 years ago
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆14Aug 21, 2023Updated 2 years ago
- USBTMC DAC firmware for the stm32f4 discovery board☆27Oct 19, 2014Updated 11 years ago
- Applying various image enhancement algorithms on Night Vision IR images using Xilinx Vivado☆16Oct 27, 2023Updated 2 years ago
- ☆10Dec 12, 2020Updated 5 years ago
- ☆10Nov 30, 2022Updated 3 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Converting Boolean expressions to CMOS Circuits☆11Oct 6, 2020Updated 5 years ago
- 一款Cyclone Ⅳ(EP4CE6E22C8N)的FPGA板，板载JTAG下载电路、HDMI(output)、UART、SDRAM、TFT-LCD等☆17Jun 29, 2023Updated 3 years ago
- FPGA based FM radio with traditional IF architecture and digital IQ demodulation☆24Oct 1, 2024Updated last year
- Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware☆13Aug 24, 2020Updated 5 years ago
- O'Reilly Course, In-Memory Computing Essentials☆10Oct 16, 2020Updated 5 years ago
- An open-source quantum automatic test generator.☆15Apr 14, 2026Updated 4 months ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 6 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆44Nov 27, 2022Updated 3 years ago
- HYF's high quality verilog codes☆19Dec 25, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Simple RiscV core for academic purpose.☆22Apr 29, 2020Updated 6 years ago
- This place provide different SRAM cells netlist to be simulated with HSpice tool in sub-20nm FinFET technologies.☆12Dec 31, 2020Updated 5 years ago
- Design of BandGapReference Circuit using Sky130 PDK☆11Oct 30, 2021Updated 4 years ago
- Reference designs and firmware for open-source RISC-V core implementation on MX10 and SpiderSoM☆18Nov 11, 2022Updated 3 years ago
- An open silicon CHERIoT Ibex microcontroller chip☆19May 23, 2025Updated last year
- Lecture Material on Deep Learning Inference using FPGA☆13Jun 9, 2020Updated 6 years ago
- ☆10Dec 15, 2023Updated 2 years ago