xupgit / compute_acceleration
☆12Updated 4 years ago
Alternatives and similar repositories for compute_acceleration:
Users that are interested in compute_acceleration are comparing it to the libraries listed below
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆18Updated 8 years ago
- CNN accelerator☆28Updated 7 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆64Updated last month
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ☆26Updated 5 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆29Updated 4 years ago
- DASS HLS Compiler☆29Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆61Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Open Source PHY v2☆27Updated 11 months ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- Algorithmic C Machine Learning Library☆22Updated 3 months ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 6 months ago
- ☆21Updated this week
- ☆25Updated last week
- HLS for Networks-on-Chip☆33Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆36Updated 6 months ago
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆15Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆49Updated 7 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆45Updated last week
- ☆28Updated 5 years ago
- A tool to generate optimized hardware files for univariate functions.☆27Updated 11 months ago