xupgit / compute_accelerationLinks
☆12Updated 5 years ago
Alternatives and similar repositories for compute_acceleration
Users that are interested in compute_acceleration are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- Project repo for the POSH on-chip network generator☆48Updated 4 months ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆42Updated last month
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 5 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated last month
- SRAM☆22Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- CNN accelerator☆27Updated 8 years ago
- Hardware Accelerators (HwAs) constructed in Vivado HLS☆20Updated 8 years ago
- A collection of tools for working with Chisel-generated hardware in SystemC☆16Updated 5 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆126Updated 2 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆65Updated 5 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆51Updated 8 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- Ratatoskr NoC Simulator☆27Updated 4 years ago
- ☆27Updated 5 years ago
- A tool to generate optimized hardware files for univariate functions.☆29Updated last year
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 4 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆57Updated last week
- Next generation CGRA generator☆112Updated last week
- DASS HLS Compiler☆29Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆9Updated 4 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago