xupgit / compute_acceleration
☆12Updated 5 years ago
Alternatives and similar repositories for compute_acceleration
Users that are interested in compute_acceleration are comparing it to the libraries listed below
Sorting:
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- RISC-V ISA based 32-bit processor written in HLS☆17Updated 5 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- ☆20Updated 5 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- ☆27Updated 5 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- The Verilog source code for DRUM approximate multiplier.☆30Updated 2 years ago
- ☆27Updated last month
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆15Updated last year
- CNN accelerator☆27Updated 7 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆54Updated 3 months ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆30Updated 5 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- ☆44Updated 5 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆38Updated 8 months ago
- Project repo for the POSH on-chip network generator☆45Updated last month
- General Purpose AXI Direct Memory Access☆49Updated last year
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- DASS HLS Compiler☆29Updated last year
- Algorithmic C Machine Learning Library☆23Updated 4 months ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆18Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆49Updated 4 years ago