Alternatives and similar repositories for RISC-V-On-PYNQ:

Users that are interested in RISC-V-On-PYNQ are comparing it to the libraries listed below

• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆83Updated last year
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆130Updated 8 months ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆98Updated 2 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆131Updated 2 months ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆103Updated 6 years ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆146Updated 7 months ago
• Xilinx / Vivado-Design-Tutorials
  ☆178Updated last month
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆167Updated 2 years ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆124Updated 10 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆112Updated 5 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆66Updated last year
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆83Updated 9 months ago
• hillhao / PYNQ-project
  PYNQ, Neural network Language model, Overlay
  ☆105Updated 5 years ago
• cathalmccabe / PYNQ_tutorials
  ☆77Updated last year
• chenhaoc / cnnhwpe
  ☆64Updated 2 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆160Updated 3 months ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆209Updated last year
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆300Updated 9 months ago
• alan4186 / Hardware-CNN
  A convolutional neural network implemented in hardware (verilog)
  ☆155Updated 7 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆233Updated last year
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆79Updated 5 years ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆154Updated 2 months ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆88Updated last year
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆204Updated 4 years ago
• PeterOgden / overlay_tutorial
  Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
  ☆39Updated 3 years ago
• Xilinx / XilinxBoardStore
  ☆273Updated last week
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆84Updated 3 years ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆189Updated 4 months ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆106Updated 10 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆70Updated 8 months ago