Board files to build Ultra 96 PYNQ image
☆157Sep 14, 2025Updated 6 months ago
Alternatives and similar repositories for Ultra96-PYNQ
Users that are interested in Ultra96-PYNQ are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- DPU on PYNQ☆243Aug 12, 2025Updated 7 months ago
- Networking Overlay on PYNQ☆50Mar 5, 2019Updated 7 years ago
- Avnet Board Definition Files☆141Jan 12, 2026Updated 2 months ago
- Ultra96 PYNQ入门之一次简单的总结☆14May 21, 2020Updated 5 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Apr 28, 2020Updated 5 years ago
- Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2☆19Apr 11, 2020Updated 5 years ago
- Computer Vision Overlays on Pynq☆190Oct 4, 2019Updated 6 years ago
- Firmware binaries for Microchip ATWILC Wireless Devices (ATWILC1000 & ATWILC3000)☆16Feb 23, 2026Updated last month
- Ubuntu 20.04 Desktop for Ultra96/Ultra96-V2☆11Nov 27, 2021Updated 4 years ago
- Python Productivity for ZYNQ☆2,287Mar 2, 2026Updated 3 weeks ago
- DAC System Design Contest 2020☆29Jun 11, 2020Updated 5 years ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆63Mar 27, 2025Updated 11 months ago
- ☆91Apr 15, 2020Updated 5 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107May 5, 2018Updated 7 years ago
- NPUEval is an LLM evaluation dataset written specifically to target AIE kernel code generation on RyzenAI hardware.☆30Nov 8, 2025Updated 4 months ago
- ☆35Sep 12, 2019Updated 6 years ago
- ☆250Oct 13, 2020Updated 5 years ago
- ☆23Oct 7, 2021Updated 4 years ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆34Sep 19, 2018Updated 7 years ago
- ☆117Jul 15, 2021Updated 4 years ago
- Used for overriding files generated by PetaLinux with Avnet board specific configurations.☆12Mar 24, 2025Updated last year
- Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.☆1,744Feb 24, 2026Updated last month
- Vitis HLS Library for FINN☆216Feb 25, 2026Updated last month
- PYNQ support and examples for Kria SOMs☆126Aug 20, 2024Updated last year
- This project is trying to create a base vitis platform to run with DPU☆49Jul 8, 2020Updated 5 years ago
- ☆15Apr 11, 2025Updated 11 months ago
- Social Disatancing Monitor using yolov3 and DPU HW acceleration for Xilinx adaptive computing challenge 2020☆12Feb 17, 2023Updated 3 years ago
- Train and deploy LUT-based neural networks on FPGAs☆107Jun 12, 2024Updated last year
- Adding PR to the PYNQ Overlay☆19Apr 19, 2017Updated 8 years ago
- Quantized Neural Networks (QNNs) on PYNQ☆703Jan 4, 2022Updated 4 years ago
- ☆466Sep 10, 2024Updated last year
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆337Jul 9, 2019Updated 6 years ago
- 2021 Xilinx China Winter Camp☆11Mar 12, 2021Updated 5 years ago
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆108Oct 31, 2022Updated 3 years ago
- Dataflow compiler for QNN inference on FPGAs☆954Updated this week
- Public resources available for Xilinx MPSOC+ and SDSOC hardware☆18May 26, 2017Updated 8 years ago
- ☆13Aug 14, 2023Updated 2 years ago
- ☆19Dec 18, 2024Updated last year
- IIoT-SPYN gives users the ability to control, monitor, capture data, visualize and analyze industrial grade motors☆44Mar 19, 2020Updated 6 years ago