Alternatives and similar repositories for PYNQ_Bootcamp

Users that are interested in PYNQ_Bootcamp are comparing it to the libraries listed below

• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆31Updated 5 years ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆106Updated 2 years ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆157Updated 3 weeks ago
• cathalmccabe / PYNQ_tutorials
  ☆97Updated last year
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆107Updated 7 years ago
• Xilinx / Kria-PYNQ
  PYNQ support and examples for Kria SOMs
  ☆115Updated last year
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆99Updated last year
• Xilinx / RFNoC-HLS-NeuralNet
  ☆109Updated 6 years ago
• xupgit / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆103Updated 5 years ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 3 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆52Updated 2 years ago
• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆40Updated 3 years ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆228Updated last month
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆234Updated last month
• Xilinx / LSTM-PYNQ
  ☆90Updated 5 years ago
• sfox14 / pynq-ekf
  A multi-board Extended Kalman Filter (EKF)
  ☆32Updated 7 years ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆117Updated 4 years ago
• Xilinx / PYNQ-Networking
  Networking Overlay on PYNQ
  ☆50Updated 6 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆92Updated this week
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆208Updated last week
• hillhao / PYNQ-project
  PYNQ, Neural network Language model, Overlay
  ☆110Updated 6 years ago
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆112Updated 5 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆86Updated 2 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆66Updated 8 years ago
• Xilinx / PYNQ_Peripherals
  ☆23Updated 3 years ago
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆91Updated 9 months ago
• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆48Updated last year
• Xilinx / Vitis_Model_Composer
  Vitis Model Composer Examples and Tutorials
  ☆107Updated last week
• awai54st / LUTNet
  ☆59Updated 5 years ago