nandland / spi-slaveLinks
SPI Slave for FPGA in Verilog and VHDL
☆210Updated last year
Alternatives and similar repositories for spi-slave
Users that are interested in spi-slave are comparing it to the libraries listed below
Sorting:
- SPI Master for FPGA - VHDL and Verilog☆297Updated 2 years ago
- Verilog UART☆178Updated 12 years ago
- Verilog SPI master and slave☆57Updated 9 years ago
- I2C Master and Slave☆38Updated 10 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆363Updated last year
- Vivado诸多IP,包括图像处理等☆225Updated last year
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆72Updated 4 years ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆186Updated last year
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆60Updated 4 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆154Updated 5 months ago
- A full-speed device-side USB peripheral core written in Verilog.☆236Updated 2 years ago
- I2C controller core☆47Updated 2 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆241Updated last year
- Verilog UART☆502Updated 5 months ago
- Verilog digital signal processing components☆150Updated 2 years ago
- FPGA Logic Analyzer and GUI☆134Updated 2 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。☆301Updated last year
- A DDR3 memory controller in Verilog for various FPGAs☆502Updated 3 years ago
- SDRAM controller with AXI4 interface☆96Updated 6 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆87Updated 2 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- Fixed Point Math Library for Verilog☆141Updated 11 years ago
- 视频旋转(2019FPGA大赛)☆35Updated 5 years ago
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆345Updated 2 weeks ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- ☆72Updated 4 years ago
- Cortex M0 based SoC☆74Updated 3 years ago
- AHB3-Lite Interconnect☆90Updated last year