Alternatives and similar repositories for spi-slave

Users that are interested in spi-slave are comparing it to the libraries listed below

• nandland / spi-master
  SPI Master for FPGA - VHDL and Verilog
  ☆307Updated 2 years ago
• jamieiles / uart
  Verilog UART
  ☆186Updated 12 years ago
• csus-senior-design / i2c
  I2C Master and Slave
  ☆37Updated 10 years ago
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆143Updated 2 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆158Updated 8 months ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆76Updated 4 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆159Updated 3 years ago
• WangXuan95 / FPGA-DDR-SDRAM
  An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
  ☆194Updated 2 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆388Updated last month
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆528Updated 4 years ago
• WangXuan95 / FPGA-UART
  This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…
  ☆268Updated 2 years ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆232Updated last year
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆78Updated 13 years ago
• alexforencich / verilog-uart
  Verilog UART
  ☆514Updated 8 months ago
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆235Updated 3 years ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆144Updated 11 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆142Updated 6 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆91Updated 3 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆68Updated 4 years ago
• freecores / i2c
  I2C controller core
  ☆46Updated 2 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆61Updated 9 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆130Updated 5 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆75Updated 4 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆95Updated last year
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆390Updated 5 months ago
• benreynwar / fft-dit-fpga
  Verilog module for calculation of FFT.
  ☆188Updated 13 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆348Updated 8 years ago
• BitOpenFPGA / arl
  lists of most popular repositories for most favoured programming languages (according to StackOverflow)
  ☆81Updated 5 years ago