nandland / spi-slaveLinks
SPI Slave for FPGA in Verilog and VHDL
☆218Updated last year
Alternatives and similar repositories for spi-slave
Users that are interested in spi-slave are comparing it to the libraries listed below
Sorting:
- SPI Master for FPGA - VHDL and Verilog☆316Updated 2 years ago
- Verilog UART☆187Updated 12 years ago
- Verilog SPI master and slave☆62Updated 9 years ago
- Pipeline FFT Implementation in Verilog HDL☆153Updated 6 years ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1 控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆197Updated 2 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆279Updated 2 years ago
- I2C Master and Slave☆38Updated 10 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆159Updated 9 months ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆73Updated 5 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆77Updated 4 years ago
- Vivado诸多IP,包括图像处理等☆234Updated last year
- FPGA Logic Analyzer and GUI☆145Updated 2 years ago
- AHB3-Lite Interconnect☆107Updated last year
- Fixed Point Math Library for Verilog☆145Updated 11 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆402Updated 3 months ago
- Verilog module for calculation of FFT.☆190Updated 13 years ago
- Verilog digital signal processing components☆162Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆542Updated 4 years ago
- A simple implementation of a UART modem in Verilog.☆168Updated 4 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Verilog UART☆515Updated 9 months ago
- A full-speed device-side USB peripheral core written in Verilog.☆235Updated 3 years ago
- Cortex M0 based SoC☆75Updated 4 years ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- 视频旋转(2019FPGA大赛)☆37Updated 5 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Basic RISC-V Test SoC☆162Updated 6 years ago