SPI Slave for FPGA in Verilog and VHDL
☆233May 11, 2024Updated 2 years ago
Alternatives and similar repositories for spi-slave
Users that are interested in spi-slave are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SPI Master for FPGA - VHDL and Verilog☆346Aug 22, 2023Updated 2 years ago
- UART in Verilog and VHDL☆18Aug 21, 2022Updated 3 years ago
- Single Port RAM, Dual Port RAM, FIFO☆34May 17, 2022Updated 4 years ago
- Verilog I2C interface for FPGA implementation☆718Feb 27, 2025Updated last year
- Verilog SPI master and slave☆63Jan 4, 2016Updated 10 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆84Dec 7, 2020Updated 5 years ago
- Verilog UART☆202Jun 4, 2013Updated 13 years ago
- Various HDL (Verilog) IP Cores☆930Jul 1, 2021Updated 5 years ago
- Verilog UART☆575Feb 27, 2025Updated last year
- SPI master and SPI slave for FPGA written in VHDL☆185Apr 24, 2021Updated 5 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆473Feb 13, 2026Updated 6 months ago
- Interface Protocol in Verilog☆52Aug 2, 2019Updated 7 years ago
- A simple, basic, formally verified UART controller☆346Jan 29, 2024Updated 2 years ago
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Vivado诸多IP，包括图像处理等☆233Jul 28, 2024Updated 2 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆624Oct 10, 2021Updated 4 years ago
- Verilog AXI components for FPGA implementation☆2,116Feb 27, 2025Updated last year
- Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU☆17Oct 18, 2014Updated 11 years ago
- Simple RiscV core for academic purpose.☆22Apr 29, 2020Updated 6 years ago
- Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah…☆41Jan 8, 2025Updated last year
- Project in course “FPGA Design for Communication Systems”☆16Dec 30, 2023Updated 2 years ago
- AMBA bus lecture material☆548Jan 21, 2020Updated 6 years ago
- All code found on nandland is here. underconstruction.gif☆379Aug 21, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog PCI express components☆1,644Apr 26, 2024Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆157Jul 30, 2026Updated 2 weeks ago
- Hardware Description Language Translator☆19Aug 7, 2026Updated last week
- Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable☆28Mar 3, 2026Updated 5 months ago
- Verilog AXI stream components for FPGA implementation☆912Feb 27, 2025Updated last year
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆20Jan 27, 2023Updated 3 years ago
- Verilog digital signal processing components☆189Oct 30, 2022Updated 3 years ago
- Verilog Ethernet components for FPGA implementation☆3,071Feb 27, 2025Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆22Mar 22, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆137Jul 11, 2025Updated last year
- Must-have verilog systemverilog modules☆2,009Mar 12, 2026Updated 5 months ago
- synthesiseable ieee 754 floating point library in verilog☆754Mar 13, 2023Updated 3 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…☆344Sep 14, 2023Updated 2 years ago
- Verilog library for ASIC and FPGA designers☆1,436May 8, 2024Updated 2 years ago
- Gigabit Ethernet UDP communication driver☆84Jul 26, 2019Updated 7 years ago