SPI Slave for FPGA in Verilog and VHDL
☆231May 11, 2024Updated 2 years ago
Alternatives and similar repositories for spi-slave
Users that are interested in spi-slave are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SPI Master for FPGA - VHDL and Verilog☆341Aug 22, 2023Updated 2 years ago
- UART in Verilog and VHDL☆17Aug 21, 2022Updated 3 years ago
- Single Port RAM, Dual Port RAM, FIFO☆34May 17, 2022Updated 4 years ago
- Verilog I2C interface for FPGA implementation☆702Feb 27, 2025Updated last year
- Verilog SPI master and slave☆63Jan 4, 2016Updated 10 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Various HDL (Verilog) IP Cores☆912Jul 1, 2021Updated 4 years ago
- Verilog UART☆199Jun 4, 2013Updated 13 years ago
- Verilog UART☆570Feb 27, 2025Updated last year
- SPI master and SPI slave for FPGA written in VHDL☆183Apr 24, 2021Updated 5 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆457Feb 13, 2026Updated 4 months ago
- Interface Protocol in Verilog☆52Aug 2, 2019Updated 6 years ago
- A simple, basic, formally verified UART controller☆341Jan 29, 2024Updated 2 years ago
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆601Oct 10, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verilog AXI components for FPGA implementation☆2,075Feb 27, 2025Updated last year
- Vivado诸多IP,包括图像处理等☆235Jul 28, 2024Updated last year
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆80Dec 7, 2020Updated 5 years ago
- Simple RiscV core for academic purpose.☆23Apr 29, 2020Updated 6 years ago
- Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah…☆41Jan 8, 2025Updated last year
- Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU☆16Oct 18, 2014Updated 11 years ago
- AMBA bus lecture material☆534Jan 21, 2020Updated 6 years ago
- Verilog PCI express components☆1,610Apr 26, 2024Updated 2 years ago
- All code found on nandland is here. underconstruction.gif☆374Aug 21, 2022Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆154Updated this week
- FPGA工程合集-涉及图像、通信、接口、算法等,详见WIKI☆12Sep 7, 2024Updated last year
- ☆10Mar 11, 2022Updated 4 years ago
- Project in course “FPGA Design for Communication Systems”☆16Dec 30, 2023Updated 2 years ago
- Verilog AXI stream components for FPGA implementation☆895Feb 27, 2025Updated last year
- Hardware Description Language Translator☆19Jun 9, 2026Updated last week
- Verilog digital signal processing components☆184Oct 30, 2022Updated 3 years ago
- Verilog Ethernet components for FPGA implementation☆2,988Feb 27, 2025Updated last year
- Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable☆27Mar 3, 2026Updated 3 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆133Jul 11, 2025Updated 11 months ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆18Jan 27, 2023Updated 3 years ago
- Must-have verilog systemverilog modules☆1,973Mar 12, 2026Updated 3 months ago
- synthesiseable ieee 754 floating point library in verilog☆743Mar 13, 2023Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆22Mar 22, 2023Updated 3 years ago
- Gigabit Ethernet UDP communication driver☆84Jul 26, 2019Updated 6 years ago
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago