nandland / spi-slave
SPI Slave for FPGA in Verilog and VHDL
☆169Updated 4 months ago
Related projects: ⓘ
- SPI Master for FPGA - VHDL and Verilog☆247Updated last year
- I2C Master and Slave☆28Updated 9 years ago
- Verilog UART☆118Updated 11 years ago
- Vivado诸多IP,包括图像处理等☆157Updated last month
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆104Updated 4 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆243Updated 4 months ago
- An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。☆203Updated last year
- AHB3-Lite Interconnect☆81Updated 4 months ago
- Verilog SPI master and slave☆45Updated 8 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆206Updated last year
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆66Updated 3 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆344Updated 2 years ago
- SPI master and SPI slave for FPGA written in VHDL☆162Updated 3 years ago
- Interface Protocol in Verilog☆47Updated 5 years ago
- WISHBONE SD Card Controller IP Core☆114Updated 2 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆134Updated last year
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆87Updated 6 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆72Updated last year
- ☆60Updated 3 years ago
- Cortex M0 based SoC☆68Updated 3 years ago
- lists of most popular repositories for most favoured programming languages (according to StackOverflow)☆72Updated 3 years ago
- Gigabit Ethernet UDP communication driver☆68Updated 5 years ago
- Fixed Point Math Library for Verilog☆117Updated 10 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆12Updated 2 years ago
- 视频旋转(2019FPGA大赛)☆28Updated 4 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆84Updated 4 years ago
- Verilog UART☆403Updated last year
- Pipeline FFT Implementation in Verilog HDL☆71Updated 5 years ago
- An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆134Updated last year
- Basic RISC-V Test SoC☆102Updated 5 years ago