funningboy / uvm_axi
uvm AXI BFM(bus functional model)
☆233Updated 11 years ago
Related projects ⓘ
Alternatives and complementary repositories for uvm_axi
- Reference examples and short projects using UVM Methodology☆253Updated 2 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆154Updated 6 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆147Updated 4 years ago
- This is the main repository for all the examples for the book Practical UVM☆172Updated 4 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆171Updated last year
- UVM examples and projects☆121Updated 5 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆93Updated 6 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆104Updated 6 years ago
- VIP for AXI Protocol☆108Updated 2 years ago
- AMBA AXI VIP☆363Updated 4 months ago
- Source code repo for UVM Tutorial for Candy Lovers☆178Updated 7 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆129Updated 6 years ago
- AXI DMA 32 / 64 bits☆100Updated 10 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆111Updated 3 years ago
- Awesome ASIC design verification☆268Updated 2 years ago
- UVM AHB VIP☆77Updated 2 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆488Updated 2 years ago
- AMBA bus lecture material☆380Updated 4 years ago
- Novel GUI Based UVM Testbench Template Builder☆119Updated 3 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆89Updated 6 years ago
- Examples and reference for System Verilog Assertions☆81Updated 7 years ago
- A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology☆93Updated 10 years ago
- Yet Another Simulation Architecture☆73Updated 4 years ago
- A generic class library in SystemVerilog☆79Updated 3 years ago
- UVM 1.2 port to Python☆243Updated 8 months ago
- UVM agents☆74Updated 7 years ago
- SystemVerilog VIP for AMBA APB protocol☆67Updated 3 years ago
- 数字IC秋招项目、手撕代码☆33Updated 7 months ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆266Updated 6 months ago
- An AXI4 crossbar implementation in SystemVerilog☆123Updated this week