gillianGan / ahb_sram_masterLinks
☆19Updated 5 years ago
Alternatives and similar repositories for ahb_sram_master
Users that are interested in ahb_sram_master are comparing it to the libraries listed below
Sorting:
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆134Updated 4 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆190Updated 7 years ago
- 数字IC秋招项目、手撕代码☆39Updated last year
- AMBA bus lecture material☆495Updated 5 years ago
- IC Verification & SV Demo☆55Updated 4 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆135Updated 8 years ago
- AXI总线连接器☆105Updated 5 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆235Updated 2 years ago
- An uvm verification env for ahb2apb bridge☆58Updated 4 years ago
- uvm AXI BFM(bus functional model)☆264Updated 12 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆72Updated 3 years ago
- This is the main repository for all the examples for the book Practical UVM☆213Updated 5 years ago
- Reference examples and short projects using UVM Methodology☆286Updated 3 years ago
- VIP for AXI Protocol☆163Updated 3 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆163Updated 5 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆116Updated 8 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆160Updated 5 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆103Updated 2 years ago
- Radix-4 1024 point fft in verilog☆13Updated 5 years ago
- Awesome ASIC design verification☆340Updated 3 years ago
- AMBA AXI VIP☆438Updated last year
- UVM AHB VIP☆90Updated 3 months ago
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆15Updated 3 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆28Updated 3 years ago
- UVM examples and projects☆153Updated 6 months ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆116Updated last year
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆106Updated 4 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆194Updated last year
- Implementation of CNN using Verilog☆235Updated 8 years ago