gillianGan / ahb_sram_master
☆18Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for ahb_sram_master
- IC Verification & SV Demo☆45Updated 3 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆110Updated 3 years ago
- AXI总线连接器☆90Updated 4 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆54Updated last year
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆104Updated 6 years ago
- An uvm verification env for ahb2apb bridge☆47Updated 3 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆152Updated 6 years ago
- UVM examples and projects☆121Updated 5 years ago
- AXI DMA 32 / 64 bits☆97Updated 10 years ago
- 数字IC秋招项目、手撕代码☆33Updated 6 months ago
- SPI interface connect to APB BUS with Verilog HDL☆25Updated 3 years ago
- ahb scram controller, design and verification☆27Updated 6 years ago
- UVM AHB VIP☆75Updated 2 years ago
- VIP for AXI Protocol☆108Updated 2 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆147Updated 4 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆49Updated 2 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆93Updated 6 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆24Updated 4 years ago
- Verification IP for I2C protocol☆36Updated 3 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆69Updated last year
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆20Updated 2 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆31Updated 4 years ago
- a very simple risc_cpu verification demo with uvm☆21Updated 5 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆15Updated last year
- This is the main repository for all the examples for the book Practical UVM☆170Updated 4 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆47Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆27Updated last year
- UVM Testbench to verify serial transmission of data between SPI master and slave☆34Updated 4 years ago
- AXI Interconnect☆45Updated 3 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆33Updated 4 years ago