gillianGan / ahb_sram_master
☆18Updated 5 years ago
Alternatives and similar repositories for ahb_sram_master:
Users that are interested in ahb_sram_master are comparing it to the libraries listed below
- AXI总线连接器☆97Updated 5 years ago
- IC Verification & SV Demo☆52Updated 3 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆119Updated 3 years ago
- ARM中通过APB总线连接的UART模块☆63Updated 5 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- ahb scram controller, design and verification☆27Updated 6 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆58Updated last year
- 数字IC秋招项目、手撕代码☆34Updated 11 months ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- An uvm verification env for ahb2apb bridge☆48Updated 3 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆112Updated 7 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆87Updated last year
- AXI Interconnect☆47Updated 3 years ago
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆166Updated 6 years ago
- ☆36Updated 9 years ago
- SPI interface connect to APB BUS with Verilog HDL☆29Updated 3 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …☆27Updated 4 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆101Updated 3 months ago
- Verification IP for I2C protocol☆41Updated 3 years ago
- VIP for AXI Protocol☆124Updated 2 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆94Updated 7 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- FFT implement by verilog_测试验证已通过☆54Updated 8 years ago
- Mirror of william_william/uvm-mcdf on Gitee☆21Updated 2 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆48Updated 4 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆139Updated 6 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆42Updated 4 years ago