dadongshangu / async_FIFO

Related projects ⓘ

Alternatives and complementary repositories for async_FIFO

• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆56Updated 3 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆36Updated 3 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆76Updated 2 years ago
• flyskywalker / ahb_sramc
  ahb scram controller, design and verification
  ☆27Updated 6 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆28Updated 4 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆71Updated last year
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆34Updated 4 years ago
• Gateway91 / AHB-APB_Bridge_UVM_Env
  AHB-APB UVM Verification Environment
  ☆17Updated 9 years ago
• hjking / uvm_gen
  UVM Generator
  ☆43Updated 6 months ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆108Updated 2 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆37Updated 4 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆51Updated 7 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆34Updated 4 years ago
• muneebullashariff / apb_vip
  Verification IP for APB protocol
  ☆25Updated 4 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆47Updated 4 years ago
• MushroomZQ / RISC_VERIF_DEMO_0
  a very simple risc_cpu verification demo with uvm
  ☆22Updated 5 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆27Updated last year
• Lampro-Mellon / apb-uart-uvm-env
  ☆34Updated last year
• dpc525 / uvm_tb_gen
  generate UVM testbench using python
  ☆26Updated 6 years ago
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆16Updated 3 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆104Updated 6 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆20Updated 2 years ago
• muneebullashariff / spi_vip
  Verification IP for SPI protocol
  ☆16Updated 4 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆47Updated 3 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆46Updated 3 years ago
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆15Updated 8 months ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆49Updated 2 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆93Updated 6 years ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆28Updated 2 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆42Updated 8 months ago