Alternatives and similar repositories for async_FIFO

Users that are interested in async_FIFO are comparing it to the libraries listed below

• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆88Updated last year
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆45Updated 4 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆63Updated 4 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆32Updated 4 years ago
• flyskywalker / ahb_sramc
  ahb scram controller, design and verification
  ☆27Updated 6 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆83Updated 5 months ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆133Updated 2 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆115Updated 7 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆49Updated 4 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆44Updated 5 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆42Updated 3 years ago
• VimfulDang / APB-SPI-Controller-Verification
  UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…
  ☆12Updated 4 months ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆31Updated 2 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆25Updated 2 years ago
• gokulbalagopal / Verification-of-FIFO-using-SystemVerilog
  Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…
  ☆27Updated 6 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆38Updated 4 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆50Updated 4 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆58Updated 2 years ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆40Updated last year
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆135Updated 6 years ago
• KafCoppelia / uvm-mcdf
  Mirror of william_william/uvm-mcdf on Gitee
  ☆23Updated 2 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆40Updated 3 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆141Updated 6 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆102Updated 4 months ago
• shubhi704 / APB-Protocol
  ☆43Updated 3 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆169Updated 6 years ago
• MushroomZQ / RISC_VERIF_DEMO_0
  a very simple risc_cpu verification demo with uvm
  ☆22Updated 6 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆148Updated 5 years ago
• muneebullashariff / apb_vip
  Verification IP for APB protocol
  ☆26Updated 4 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆72Updated 3 years ago