rlin27 / BATMANNLinks
Implementation for paper "BATMANN: A Binarized-All-Through Memory-Augmented Neural Network for Efficient In-Memory Computing"
☆12Updated 4 years ago
Alternatives and similar repositories for BATMANN
Users that are interested in BATMANN are comparing it to the libraries listed below
Sorting:
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆97Updated 4 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆53Updated 4 years ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆25Updated 4 years ago
- Stochastic Computing for Deep Neural Networks☆33Updated 5 years ago
- ☆32Updated 9 months ago
- Simulator for LLM inference on an abstract 3D AIMC-based accelerator☆25Updated 4 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆46Updated 5 years ago
- ☆35Updated 5 years ago
- ☆42Updated last year
- Sparse CNN Accelerator targeting Intel FPGA☆12Updated 4 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆76Updated 10 months ago
- ☆72Updated 2 years ago
- A DAG processor and compiler for a tree-based spatial datapath.☆15Updated 3 years ago
- ☆19Updated 4 years ago
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆16Updated 4 years ago
- Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators☆11Updated 6 years ago
- Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory☆42Updated 6 years ago
- ☆11Updated last year
- Open-source of MSD framework☆16Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆92Updated last year
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆43Updated 4 years ago
- QuickEst repository: Quick Estimation of Quality of Results☆26Updated 7 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆53Updated 7 years ago
- ☆71Updated 5 years ago
- ☆82Updated 3 weeks ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆92Updated 3 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆33Updated 6 years ago
- Docker container with tools for the Timeloop/Accelergy tutorial☆22Updated last year
- Quantized Training for Convolutional Neural Networks using Xilinx Brevitas☆12Updated 3 years ago