a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog
☆24Jul 20, 2023Updated 2 years ago
Alternatives and similar repositories for ritter-soc
Users that are interested in ritter-soc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆22Mar 22, 2023Updated 3 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆35Mar 21, 2020Updated 6 years ago
- 『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ☆13Jul 30, 2019Updated 6 years ago
- Mini RISC-V SOC☆12Nov 13, 2015Updated 10 years ago
- A classic five stage pipelined processor☆13Mar 13, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- みんなのSystemVerilog☆19May 12, 2022Updated 4 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆57Aug 14, 2024Updated last year
- ☆10Feb 27, 2020Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- Social Disatancing Monitor using yolov3 and DPU HW acceleration for Xilinx adaptive computing challenge 2020☆12Feb 17, 2023Updated 3 years ago
- Alternative compiler for the J1B embedded CPU☆15Oct 31, 2020Updated 5 years ago
- Arduino Uno based signal generator for scientific applications.☆19Sep 24, 2019Updated 6 years ago
- BiSUNA framework specialized to compile for the Xilinx Alveo U50☆13Dec 3, 2020Updated 5 years ago
- ☆10Feb 8, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Demo SoC☆10Oct 17, 2023Updated 2 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 6 months ago
- Zero Gecko 110 quick start breakout board☆20Mar 23, 2014Updated 12 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- transplant several overlays to s9_pynq board☆17Oct 31, 2020Updated 5 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- ☆11Mar 12, 2024Updated 2 years ago
- Tutorial☆15Jun 13, 2020Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆23Jul 7, 2024Updated last year
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆13Jan 15, 2017Updated 9 years ago
- DeviceIO是一个驱动框架,用于封装嵌入式HAL驱动,为上层应用提供服务。☆10Jun 1, 2024Updated last year
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 5 years ago
- This is a uvm example. The video is available at https://www.bilibili.com/video/BV1yq4y177f6/☆51Mar 2, 2022Updated 4 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆21Sep 14, 2023Updated 2 years ago
- ☆15Jul 5, 2019Updated 6 years ago
- ☆15Aug 10, 2023Updated 2 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆14Feb 24, 2025Updated last year
- 这是武汉大学WHU 计算机组成与设计 RISC-V CPU 流水线设计,包括Modelsim仿真测试,vivado下FPGA(NEXYS A7)测试。☆33May 21, 2024Updated 2 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆14Jul 28, 2021Updated 4 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆20Nov 13, 2024Updated last year
- APB VIP (UVM)☆18Sep 6, 2018Updated 7 years ago
- RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.☆21Jun 3, 2023Updated 2 years ago
- ☆12Jan 19, 2022Updated 4 years ago