a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog
☆24Jul 20, 2023Updated 3 years ago
Alternatives and similar repositories for ritter-soc
Users that are interested in ritter-soc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆22Mar 22, 2023Updated 3 years ago
- Mini RISC-V SOC☆13Nov 13, 2015Updated 10 years ago
- 『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ☆13Jul 30, 2019Updated 7 years ago
- Kernel module that makes it possible to create virtual wifi devices each with a virtualized stack.☆11Dec 13, 2011Updated 14 years ago
- Example of Chisel3 Diplomacy☆11Feb 23, 2022Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- みんなのSystemVerilog☆19May 12, 2022Updated 4 years ago
- Social Disatancing Monitor using yolov3 and DPU HW acceleration for Xilinx adaptive computing challenge 2020☆12Feb 17, 2023Updated 3 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆56Aug 14, 2024Updated 2 years ago
- ☆10Feb 27, 2020Updated 6 years ago
- BiSUNA framework specialized to compile for the Xilinx Alveo U50☆13Dec 3, 2020Updated 5 years ago
- A classic five stage pipelined processor☆13Mar 13, 2024Updated 2 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 3 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Alternative compiler for the J1B embedded CPU☆15Oct 31, 2020Updated 5 years ago
- A small and simple rv32i core written in Verilog☆18Jul 29, 2022Updated 4 years ago
- ☆10Feb 8, 2023Updated 3 years ago
- CNC probe macros on one screen for LinuxCNC v2.8☆11Apr 30, 2024Updated 2 years ago
- Demo SoC☆10Oct 17, 2023Updated 2 years ago
- APB Timer Unit☆14Oct 30, 2025Updated 10 months ago
- Detection of newly drone devices, characterized by very small size. Proposal of a method that is cheaper and simpler than current methods…☆17Jul 8, 2022Updated 4 years ago
- ☆22Dec 3, 2025Updated 9 months ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆11Mar 12, 2024Updated 2 years ago
- ☆13Jan 14, 2021Updated 5 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- data preprocessing scripts for gem5 output☆19May 23, 2025Updated last year
- Tutorial☆16Jun 13, 2020Updated 6 years ago
- Synchronous FIFO Testbench☆12Apr 17, 2022Updated 4 years ago
- FIR band-pass filter using Verilog HDL.☆14Sep 7, 2026Updated 3 weeks ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆15Jul 28, 2021Updated 5 years ago
- This is a uvm example. The video is available at https://www.bilibili.com/video/BV1yq4y177f6/☆52Mar 2, 2022Updated 4 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆13Jan 15, 2017Updated 9 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆14Sep 28, 2022Updated 4 years ago
- ☆15Jul 5, 2019Updated 7 years ago
- RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by TA.☆20Jun 3, 2023Updated 3 years ago
- 这是武汉大学WHU 计算机组成与设计 RISC-V CPU 流水线设计，包括Modelsim仿真测试，vivado下FPGA(NEXYS A7)测试。☆32May 21, 2024Updated 2 years ago
- ☆32Feb 3, 2026Updated 7 months ago
- Make Vim complete like a modern editor - does the right thing. Works with Ultisnips and neocomplete.☆20Apr 15, 2017Updated 9 years ago