Blunk-electronic / M-1
An OpenSource Boundary Scan Test System (JTAG / IEEE1149.x)
☆32Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for M-1
- Utilities for the ECP5 FPGA☆18Updated 3 years ago
- USB Full-Speed core written in migen/LiteX☆41Updated 5 years ago
- ice40 USB Analyzer☆57Updated 4 years ago
- Tools and Examples for IcoBoard☆79Updated 3 years ago
- iCE40 floorplan viewer☆24Updated 6 years ago
- ☆20Updated 7 months ago
- Quickstart binaries for flashing ULX3S to factory-default state☆25Updated 2 years ago
- Python tools to interact with boundary scan-capable devices. Useful for reverse engineering, testing, etc.☆16Updated 8 years ago
- Simplified environment for litex☆13Updated 4 years ago
- Dual MikroBUS board for Upduino 2 FPGA☆17Updated 6 years ago
- My pergola FPGA projects☆30Updated 3 years ago
- Misc open FPGA flow examples☆8Updated 4 years ago
- Example of Ada code running on the PicoRV32 RISC-V CPU for FPGA☆15Updated 6 years ago
- verilog core for ws2812 leds☆31Updated 3 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆33Updated 3 years ago
- ☆57Updated last year
- XVCD implementation for ANITA. Note that "ftdi_xvc_core.c" is a generic libftdi-based MPSSE XVC handler, and is awesome.☆18Updated 4 years ago
- An all-digital GPS disciplined oscillator using MMCM phase shift.☆27Updated 2 years ago
- Yosys Plugins☆20Updated 5 years ago
- understanding the tinyfpga bootloader☆24Updated 6 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆36Updated last year
- Use ECP5 JTAG port to interact with user design☆24Updated 3 years ago
- ULX2S / ULX3S FPGA JTAG programmer & tools (Lattice XP2 / ECP5)☆22Updated last week
- ☆43Updated 7 months ago
- Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm☆32Updated 6 years ago
- HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs☆12Updated 5 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆19Updated 4 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆32Updated 3 years ago
- A Grako-based parser for IEEE 1149.1 Boundary-Scan Description Language (BSDL) files☆24Updated 3 years ago