qermit / WishboneAXI
Wishbone to AXI bridge (VHDL)
☆40Updated 5 years ago
Alternatives and similar repositories for WishboneAXI:
Users that are interested in WishboneAXI are comparing it to the libraries listed below
- Verilog wishbone components☆113Updated last year
- Wishbone interconnect utilities☆39Updated last month
- Extensible FPGA control platform☆59Updated last year
- USB Full Speed PHY☆42Updated 4 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated last week
- Small footprint and configurable JESD204B core☆41Updated 2 months ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- A Vivado IP package of the PicoRV32 RISC-V processor☆15Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- TCP/IP controlled VPI JTAG Interface.☆65Updated 2 months ago
- USB -> AXI Debug Bridge☆36Updated 3 years ago
- PicoRV☆44Updated 5 years ago
- JTAG Test Access Port (TAP)☆33Updated 10 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- USB 2.0 Device IP Core☆63Updated 7 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- UART models for cocotb☆26Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆43Updated 9 years ago
- Wishbone controlled I2C controllers☆47Updated 4 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆101Updated 3 years ago
- Another tiny RISC-V implementation☆54Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago