qermit / WishboneAXI
Wishbone to AXI bridge (VHDL)
☆40Updated 5 years ago
Alternatives and similar repositories for WishboneAXI:
Users that are interested in WishboneAXI are comparing it to the libraries listed below
- Wishbone interconnect utilities☆38Updated 7 months ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- Verilog wishbone components☆113Updated last year
- USB Full Speed PHY☆39Updated 4 years ago
- Extensible FPGA control platform☆55Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆61Updated 2 years ago
- Spen's Official OpenOCD Mirror☆48Updated 10 months ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- ☆36Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- SpinalHDL Hardware Math Library☆82Updated 6 months ago
- Minimal DVI / HDMI Framebuffer☆78Updated 4 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Verilog Repository for GIT☆31Updated 3 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 4 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆86Updated 4 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆33Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- ☆23Updated 3 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- UART 16550 core☆32Updated 10 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆64Updated 9 months ago
- FuseSoC standard core library☆124Updated 3 weeks ago