qermit / WishboneAXILinks
Wishbone to AXI bridge (VHDL)
☆44Updated 6 years ago
Alternatives and similar repositories for WishboneAXI
Users that are interested in WishboneAXI are comparing it to the libraries listed below
Sorting:
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Verilog wishbone components☆124Updated last year
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated last week
- Wishbone interconnect utilities☆43Updated 10 months ago
- USB Full Speed PHY☆48Updated 5 years ago
- Wishbone controlled I2C controllers☆55Updated last year
- Small footprint and configurable JESD204B core☆49Updated 2 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated this week
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- ☆41Updated 4 years ago
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆96Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆52Updated 2 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆42Updated last year
- FuseSoC standard core library☆150Updated last week
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Updated last year
- ☆26Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆39Updated 4 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆92Updated 3 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆69Updated 7 years ago
- Verilog Repository for GIT☆34Updated 4 years ago
- Small (Q)SPI flash memory programmer in Verilog☆66Updated 3 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆96Updated 5 years ago
- TCP/IP controlled VPI JTAG Interface.☆69Updated 11 months ago