Alternatives and similar repositories for WishboneAXI

Users that are interested in WishboneAXI are comparing it to the libraries listed below

• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆124Updated 2 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆44Updated last month
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆57Updated last year
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆50Updated 3 weeks ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆70Updated last month
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆48Updated 5 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆83Updated 5 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆47Updated last year
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆45Updated 10 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 5 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆39Updated 5 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆69Updated last year
• featherweight-ip / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 4 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated this week
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆40Updated 11 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated 2 months ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆42Updated 2 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆39Updated 4 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆115Updated last week
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆93Updated 7 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆36Updated 5 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago