ZipCPU / videozip

Related projects ⓘ

Alternatives and complementary repositories for videozip

• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆36Updated 9 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆53Updated last year
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 3 months ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated 6 months ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆26Updated 3 weeks ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆16Updated last year
• FPGA-Research-Manchester / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆26Updated 3 years ago
• andrewattwood / fuserisc
  Dual RISC-V DISC with integrated eFPGA
  ☆15Updated 3 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year
• fabriziotappero / opencores-scraper
  few python scripts to clone all IP cores from opencores.org
  ☆18Updated 10 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆36Updated 5 months ago
• efabless / caravel-lite
  ☆15Updated this week
• suoto / fpga_cores
  ☆32Updated last year
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 6 months ago
• hukenovs / tcl_for_fpga
  TCL scripts for FPGA (Xilinx)
  ☆31Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆26Updated 3 weeks ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆21Updated 5 years ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 4 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆35Updated 3 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆30Updated 3 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• bharathk005 / Verilog_projects
  HDMI + GPU-pipeline + FFT
  ☆13Updated 8 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆34Updated 3 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆12Updated last year
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆36Updated 3 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆43Updated 8 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago