ZipCPU / videozipLinks
A ZipCPU SoC for the Nexys Video board supporting video functionality
☆17Updated 6 months ago
Alternatives and similar repositories for videozip
Users that are interested in videozip are comparing it to the libraries listed below
Sorting:
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Extensible FPGA control platform☆62Updated 2 years ago
- Wishbone controlled I2C controllers☆49Updated 6 months ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 4 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Dual RISC-V DISC with integrated eFPGA☆16Updated 3 years ago
- CMod-S6 SoC☆42Updated 7 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆45Updated last year
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 5 months ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- USB -> AXI Debug Bridge☆39Updated 3 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆23Updated last week
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆35Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated last week
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 4 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- ☆32Updated 2 years ago
- TCL scripts for FPGA (Xilinx)☆32Updated 2 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- Automatic SystemVerilog linting in github actions with the help of Verible☆34Updated 7 months ago
- USB Full Speed PHY☆44Updated 5 years ago