A ZipCPU SoC for the Nexys Video board supporting video functionality
☆21Nov 13, 2024Updated last year
Alternatives and similar repositories for videozip
Users that are interested in videozip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆22Mar 22, 2023Updated 3 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆48Apr 15, 2024Updated 2 years ago
- A pipelined cordic algoithm for computing cos(angle) and sin(angle) in verilog☆19May 29, 2017Updated 9 years ago
- A Video display simulator☆185May 16, 2025Updated last year
- I2C Master Verilog module☆38Jun 1, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A ZipCPU based demonstration of the MAX1000 FPGA board☆24May 11, 2021Updated 5 years ago
- Audio Signal Processing SoC☆20Mar 13, 2018Updated 8 years ago
- A programming language for FPGAs.☆19May 5, 2018Updated 8 years ago
- A vhdl package for reading and writing bitmap files.☆12Jan 9, 2018Updated 8 years ago
- few python scripts to clone all IP cores from opencores.org☆29Jan 8, 2024Updated 2 years ago
- Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs☆21Jun 4, 2020Updated 6 years ago
- A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA☆24Sep 2, 2023Updated 2 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Testing Ibex build using Yosys and open source toolchains.☆11Oct 2, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- A wishbone controlled PWM (audio) controller☆19Jan 16, 2024Updated 2 years ago
- A Parallel Simulation Framework For Multicore Systems☆10May 20, 2017Updated 9 years ago
- ☆13Dec 23, 2022Updated 3 years ago
- FOS - FPGA Operating System☆74Oct 22, 2020Updated 5 years ago
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆13Jan 15, 2017Updated 9 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆13Sep 28, 2022Updated 3 years ago
- Cadence PCB and SCH Library and some tools☆14Jan 9, 2015Updated 11 years ago
- Xilinx Unisim Library in Verilog☆93Jul 22, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆13Sep 3, 2019Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆11Jan 27, 2022Updated 4 years ago
- ☆14Jul 16, 2026Updated 3 weeks ago
- C++ and SFML based 2D simulation RPG game☆12Feb 2, 2021Updated 5 years ago
- Make Vim complete like a modern editor - does the right thing. Works with Ultisnips and neocomplete.☆20Apr 15, 2017Updated 9 years ago
- BECE_Notes 📚 A comprehensive collection of organized study materials for Bachelor in Computer Engineering at Pokhara University. Contain…☆21Jun 21, 2026Updated last month
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆17Nov 19, 2019Updated 6 years ago
- ☆12Jan 19, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Dual-Core Out-of-Order MIPS CPU Design☆24May 8, 2025Updated last year
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 5 years ago
- An Open Source Link Protocol and Controller☆29Jul 26, 2021Updated 5 years ago
- Flask app to use Google Contacts as a phone directory for Cisco 79xx IP phones.☆19Nov 14, 2013Updated 12 years ago
- GPS Disciplined Oscillator for high-precision timekeeping. More accurate than my Rubidium-based atomic clock.☆33Jun 9, 2019Updated 7 years ago
- DDR3 controller for nMigen (WIP)☆14Dec 25, 2023Updated 2 years ago
- NeMo - A hardware agnostic neuromorphic processor simulation model built on ROSS☆14Aug 11, 2020Updated 5 years ago