sjohann81 / hf-riscLinks
HF-RISC SoC
☆36Updated last month
Alternatives and similar repositories for hf-risc
Users that are interested in hf-risc are comparing it to the libraries listed below
Sorting:
- M-extension for RISC-V cores.☆31Updated 7 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆47Updated last year
- ☆59Updated 3 years ago
- RISC-V Nox core☆66Updated 3 months ago
- A pipelined RISC-V processor☆57Updated last year
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 5 months ago
- Wishbone interconnect utilities☆41Updated 5 months ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- ☆33Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated last month
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- Platform Level Interrupt Controller☆41Updated last year
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆88Updated 5 years ago
- BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …☆25Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Updated 3 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated last week
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆49Updated 8 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆62Updated 5 months ago
- Demo SoC for SiliconCompiler.☆59Updated last month
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆32Updated last month
- Open source ISS and logic RISC-V 32 bit project☆54Updated last month
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- An implementation of RISC-V☆35Updated last week