Alternatives and similar repositories for hf-risc:

Users that are interested in hf-risc are comparing it to the libraries listed below

• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆31Updated 2 months ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 4 months ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 4 years ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆38Updated 10 months ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated 5 months ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 3 months ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆43Updated 4 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆51Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated last month
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆55Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 10 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated 2 weeks ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆44Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆88Updated 2 weeks ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated 8 months ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆18Updated 2 years ago
• armleo / ArmleoCPU
  ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set
  ☆6Updated 2 years ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated last week
• zeeshanrafique23 / mdu
  M-extension for RISC-V cores.
  ☆29Updated 4 months ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆28Updated last week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆18Updated 9 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆78Updated this week
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆40Updated last year