Alternatives and similar repositories for hf-risc:

Users that are interested in hf-risc are comparing it to the libraries listed below

• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆50Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 8 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated last week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 2 months ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆87Updated 5 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 3 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆43Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆49Updated 5 years ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• dovebutch / tlv-comp
  ☆26Updated this week
• openrisc / or1k_marocchino
  OpenRISC processor IP core based on Tomasulo algorithm
  ☆31Updated 3 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆28Updated 4 years ago
• mattvenn / gtkwave-python-filter-process
  ☆33Updated 4 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆36Updated 9 months ago
• schoeberl / wildcat
  An implementation of RISC-V
  ☆21Updated last week
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated last year
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆40Updated last year
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆52Updated last week
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆73Updated 4 years ago
• bobbl / rudolv
  RISC-V processor
  ☆28Updated 2 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆44Updated 3 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 6 months ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆43Updated last year
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆63Updated 5 years ago