sjohann81 / hf-riscLinks
HF-RISC SoC
☆37Updated this week
Alternatives and similar repositories for hf-risc
Users that are interested in hf-risc are comparing it to the libraries listed below
Sorting:
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆48Updated last year
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated 2 months ago
- RISC-V Nox core☆68Updated 2 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- M-extension for RISC-V cores.☆31Updated 10 months ago
- Open source ISS and logic RISC-V 32 bit project☆58Updated 3 months ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 9 months ago
- Demo SoC for SiliconCompiler.☆61Updated last week
- A Python package for generating HDL wrappers and top modules for HDL sources☆36Updated 2 weeks ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆94Updated this week
- ☆61Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 9 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- Mathematical Functions in Verilog☆95Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated 11 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆110Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆20Updated 2 years ago
- A simple DDR3 memory controller☆59Updated 2 years ago
- ☆42Updated 3 years ago
- Open FPGA Modules☆24Updated 11 months ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Drawio => VHDL and Verilog☆57Updated last year
- Wishbone interconnect utilities☆41Updated 7 months ago