Alternatives and similar repositories for riscduino:

Users that are interested in riscduino are comparing it to the libraries listed below

• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆254Updated 2 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆89Updated 2 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆173Updated last year
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆176Updated last week
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆133Updated last month
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆121Updated 6 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆166Updated 5 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆144Updated 10 months ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆95Updated last month
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆114Updated 6 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆85Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆274Updated last week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆74Updated this week
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆124Updated 4 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆89Updated 3 weeks ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆265Updated 4 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆128Updated 3 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆65Updated 4 months ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆83Updated last month
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆138Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆123Updated last month
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆113Updated 6 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆80Updated this week
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆197Updated 2 months ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆101Updated 11 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆133Updated 3 weeks ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆133Updated 2 years ago
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆153Updated 3 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆73Updated 2 years ago