Alternatives and similar repositories for riscduino

Users that are interested in riscduino are comparing it to the libraries listed below

• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆101Updated last month
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆166Updated 6 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆194Updated last month
• jamieiles / uart
  Verilog UART
  ☆190Updated 12 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆113Updated last year
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆118Updated 2 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆282Updated 5 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆170Updated 4 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆134Updated 7 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 6 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆189Updated last week
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆318Updated 11 months ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆168Updated 3 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated 2 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆312Updated 3 weeks ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆214Updated 3 weeks ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆125Updated 5 years ago
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆99Updated 6 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆80Updated 2 weeks ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆145Updated last week
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆289Updated last month
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 5 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 6 years ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆135Updated last month
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆132Updated 5 years ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆146Updated 2 years ago
• HDLForBeginners / Examples
  ☆115Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆68Updated 5 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆132Updated 3 months ago