dineshannayya / riscduinoLinks
Arduino compatible Risc-V Based SOC
☆156Updated last year
Alternatives and similar repositories for riscduino
Users that are interested in riscduino are comparing it to the libraries listed below
Sorting:
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated 2 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆94Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated 2 months ago
- Basic RISC-V Test SoC☆141Updated 6 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆277Updated 5 years ago
- FuseSoC standard core library☆147Updated 3 months ago
- A simple implementation of a UART modem in Verilog.☆155Updated 3 years ago
- ☆94Updated last month
- Verilog implementation of a RISC-V core☆124Updated 6 years ago
- CORE-V Family of RISC-V Cores☆294Updated 7 months ago
- Verilog UART☆180Updated 12 years ago
- VeeR EL2 Core☆298Updated this week
- RISC-V System on Chip Template☆159Updated last month
- Fabric generator and CAD tools.☆197Updated last week
- Simple 8-bit UART realization on Verilog HDL.☆109Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆156Updated 2 months ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- RISC-V Verification Interface☆103Updated 3 months ago
- Verilog digital signal processing components☆155Updated 2 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆137Updated last month
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 2 months ago
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 6 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated last week
- RISC-V Debug Support for our PULP RISC-V Cores☆270Updated 4 months ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 6 years ago
- Generic Register Interface (contains various adapters)☆128Updated last month
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆48Updated 2 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆108Updated last year
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆347Updated 6 months ago