dineshannayya / riscduinoLinks
Arduino compatible Risc-V Based SOC
☆154Updated last year
Alternatives and similar repositories for riscduino
Users that are interested in riscduino are comparing it to the libraries listed below
Sorting:
- Verilog UART☆177Updated 12 years ago
- A simple implementation of a UART modem in Verilog.☆148Updated 3 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆184Updated 3 weeks ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆117Updated 3 weeks ago
- Basic RISC-V Test SoC☆139Updated 6 years ago
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- Verilog implementation of a RISC-V core☆123Updated 6 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆98Updated last month
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆273Updated 5 years ago
- ☆98Updated last year
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆131Updated 5 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆103Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆154Updated last month
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆127Updated 2 weeks ago
- Verilog digital signal processing components☆146Updated 2 years ago
- RISC-V System on Chip Template☆158Updated last week
- FuseSoC standard core library☆146Updated 2 months ago
- Fabric generator and CAD tools.☆192Updated last week
- CORE-V Family of RISC-V Cores☆285Updated 5 months ago
- VeeR EL2 Core☆292Updated 2 weeks ago
- RISC-V Verification Interface☆100Updated 2 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆140Updated 2 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆138Updated 3 weeks ago
- ☆89Updated this week
- Generic Register Interface (contains various adapters)☆124Updated last month
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆85Updated 2 years ago