dineshannayya / riscduino
Arduino compatible Risc-V Based SOC
☆148Updated 10 months ago
Alternatives and similar repositories for riscduino
Users that are interested in riscduino are comparing it to the libraries listed below
Sorting:
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆176Updated 2 weeks ago
- VeeR EL2 Core☆276Updated 2 weeks ago
- Basic RISC-V Test SoC☆122Updated 6 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated last week
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆145Updated 11 months ago
- Generic Register Interface (contains various adapters)☆117Updated 7 months ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆91Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆83Updated this week
- FuseSoC standard core library☆136Updated last month
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆99Updated last month
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆126Updated 5 years ago
- Fabric generator and CAD tools☆182Updated this week
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆268Updated 4 years ago
- RISC-V Verification Interface☆90Updated 2 months ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆157Updated 3 years ago
- Verilog UART☆164Updated 11 years ago
- CORE-V Family of RISC-V Cores☆265Updated 3 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 4 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆91Updated 2 weeks ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆90Updated this week
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆88Updated last year
- ☆111Updated 2 years ago
- Simple 8-bit UART realization on Verilog HDL.☆102Updated last year
- Verilog digital signal processing components☆135Updated 2 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆252Updated 3 weeks ago
- ☆85Updated 2 months ago
- RISC-V System on Chip Template☆158Updated this week
- Open-source high performance AXI4-based HyperRAM memory controller☆74Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 5 months ago