dineshannayya / riscduinoLinks
Arduino compatible Risc-V Based SOC
☆155Updated last year
Alternatives and similar repositories for riscduino
Users that are interested in riscduino are comparing it to the libraries listed below
Sorting:
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆187Updated last month
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆94Updated last week
- Basic RISC-V Test SoC☆140Updated 6 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆120Updated last month
- A simple implementation of a UART modem in Verilog.☆153Updated 3 years ago
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆96Updated 2 months ago
- Verilog UART☆178Updated 12 years ago
- Simple 8-bit UART realization on Verilog HDL.☆110Updated last year
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆104Updated last year
- CORE-V Family of RISC-V Cores☆289Updated 6 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆155Updated last month
- Generic Register Interface (contains various adapters)☆126Updated 3 weeks ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆123Updated 3 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆141Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆65Updated 5 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆131Updated last week
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- RISC-V System on Chip Template☆159Updated last week
- Verilog digital signal processing components☆151Updated 2 years ago
- FuseSoC standard core library☆147Updated 3 months ago
- Fabric generator and CAD tools.☆194Updated last week
- Verilog implementation of a RISC-V core☆123Updated 6 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆108Updated last week
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆139Updated last month
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆274Updated 5 years ago
- ☆90Updated last week
- ☆99Updated last year
- RISC-V Debug Support for our PULP RISC-V Cores☆270Updated 4 months ago
- RISC-V Verification Interface☆101Updated 2 months ago
- VeeR EL2 Core☆296Updated this week