Alternatives and similar repositories for cohdl

Users that are interested in cohdl are comparing it to the libraries listed below

• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆46Updated this week
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 7 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated 2 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated 2 weeks ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 4 months ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆17Updated 2 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆156Updated 3 months ago
• VHDL / Compliance-Tests
  Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
  ☆32Updated 7 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated 2 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆36Updated 2 weeks ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆47Updated last year
• pieter3d / simview
  ☆80Updated this week
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆60Updated last year
• aignacio / nox
  RISC-V Nox core
  ☆68Updated 2 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆80Updated 3 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 5 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆111Updated 4 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆54Updated 2 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 3 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆84Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated 11 months ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 2 months ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆47Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆162Updated last week
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆79Updated 3 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆35Updated last week
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆21Updated 4 years ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆65Updated 2 weeks ago