🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
☆122Sep 16, 2026Updated last week
Alternatives and similar repositories for marlin
Users that are interested in marlin are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Rust bindings for CIRCT☆19Apr 20, 2024Updated 2 years ago
- A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://codeberg.org/spade-lang/sp…☆91Updated this week
- Verilator Porcelain☆48Nov 7, 2023Updated 2 years ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆146Aug 23, 2026Updated last month
- A programming language for writing constraint-based integrated circuit layout generators☆17Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Veryl: A Modern Hardware Description Language☆1,040Updated this week
- ☆36Updated this week
- design and verification of asynchronous circuits☆52Sep 10, 2026Updated 2 weeks ago
- ☆15Dec 9, 2025Updated 9 months ago
- Meno is a tool for visualizing hierarchical data, such as synthesized circuit sizes. It can be built into a single, standalone HTML file.…☆21Nov 3, 2025Updated 10 months ago
- Rust Test Bench - write HDL tests in Rust.☆27Nov 28, 2022Updated 3 years ago
- 21st century electronic design automation tools, written in Rust.☆37Updated this week
- A Hardware Description Language based on the Rust Programming Language☆330Apr 21, 2026Updated 5 months ago
- [MIGRATED to https://codeberg.org/prjunnamed/prjunnamed] End-to-end synthesis and P&R toolchain☆95Mar 12, 2026Updated 6 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆23Aug 31, 2026Updated 3 weeks ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆63Oct 27, 2024Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆123Apr 1, 2024Updated 2 years ago
- Block diagrams in ASCII☆18Oct 17, 2025Updated 11 months ago
- Nix flake for more up-to-date versions of EDA tools☆34Updated this week
- RTLMeter benchmark suite☆33Sep 18, 2026Updated last week
- LL(k) and LALR(1) parser generator for Rust and C#☆236Updated this week
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- ☆30Oct 16, 2022Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- High level synthesis language for hardware design☆106Updated this week
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆80Updated this week
- CIRCT and Yosys interoperability, demonstrated with CHISEL☆18Feb 3, 2026Updated 7 months ago
- A collection of datapath circuit design and verification benchmarks☆19Aug 24, 2026Updated last month
- Modern GTKWave alternative☆53May 30, 2026Updated 3 months ago
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆41Jan 16, 2025Updated last year
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Dec 3, 2024Updated last year
- ☆18Jul 12, 2024Updated 2 years ago
- ☆28Dec 4, 2025Updated 9 months ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Open-source RTL logic simulator with CUDA acceleration☆302Sep 30, 2025Updated 11 months ago
- ☆22Sep 26, 2025Updated 11 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 3 months ago
- MLIR-in as a compiler stack for ucb-bar☆19Sep 17, 2026Updated last week
- Fearless hardware design☆210Jul 23, 2026Updated 2 months ago
- A Lean-embedded framework to verify Verilog modules☆15Updated this week
- Yosys RTLIL dialect for MLIR☆24Jun 12, 2025Updated last year