🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
☆111May 3, 2026Updated 2 months ago
Alternatives and similar repositories for marlin
Users that are interested in marlin are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Rust bindings for CIRCT☆17Apr 20, 2024Updated 2 years ago
- A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spad…☆71Updated this week
- Verilator Porcelain☆49Nov 7, 2023Updated 2 years ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆136Updated this week
- A programming language for writing constraint-based integrated circuit layout generators☆17Jun 17, 2026Updated last month
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Veryl: A Modern Hardware Description Language☆987Updated this week
- ☆30Jun 17, 2026Updated last month
- design and verification of asynchronous circuits☆51Jul 9, 2026Updated 2 weeks ago
- ☆15Dec 9, 2025Updated 7 months ago
- Meno is a tool for visualizing hierarchical data, such as synthesized circuit sizes. It can be built into a single, standalone HTML file.…☆20Nov 3, 2025Updated 8 months ago
- Rust Test Bench - write HDL tests in Rust.☆27Nov 28, 2022Updated 3 years ago
- 21st century electronic design automation tools, written in Rust.☆37Updated this week
- A Hardware Description Language based on the Rust Programming Language☆321Apr 21, 2026Updated 3 months ago
- ☆21Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆61Oct 27, 2024Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆122Apr 1, 2024Updated 2 years ago
- Block diagrams in ASCII☆18Oct 17, 2025Updated 9 months ago
- RTLMeter benchmark suite☆31Updated this week
- Nix flake for more up-to-date versions of EDA tools☆31Updated this week
- LL(k) and LALR(1) parser generator for Rust and C#☆236Updated this week
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- ☆30Oct 16, 2022Updated 3 years ago
- High level synthesis language for hardware design☆100Jun 10, 2026Updated last month
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆76Updated this week
- CIRCT and Yosys interoperability, demonstrated with CHISEL☆17Feb 3, 2026Updated 5 months ago
- A collection of datapath circuit design and verification benchmarks☆19Jul 9, 2026Updated 2 weeks ago
- Modern GTKWave alternative☆48May 30, 2026Updated last month
- The Next-gen Language & Compiler Powering Efficient Hardware Design☆39Jan 16, 2025Updated last year
- VS Code based debugger for hardware designs in Amaranth or Verilog☆39Dec 3, 2024Updated last year
- ☆18Jul 12, 2024Updated 2 years ago
- ☆27Dec 4, 2025Updated 7 months ago
- Open-source RTL logic simulator with CUDA acceleration☆288Sep 30, 2025Updated 9 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆22Sep 26, 2025Updated 10 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆478Jun 10, 2026Updated last month
- MLIR-in as a compiler stack for ucb-bar☆18Updated this week
- Fearless hardware design☆205Updated this week
- A Lean-embedded framework to verify Verilog modules☆15Jul 3, 2026Updated 3 weeks ago
- Yosys RTLIL dialect for MLIR☆23Jun 12, 2025Updated last year
- A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding☆22Mar 3, 2025Updated last year