π¦ No-nonsense hardware testing/simulation in Rust π οΈ | Verilog, Spade, Veryl
β91Feb 27, 2026Updated last week
Alternatives and similar repositories for marlin
Users that are interested in marlin are comparing it to the libraries listed below
Sorting:
- Verilator Porcelainβ49Nov 7, 2023Updated 2 years ago
- 21st century electronic design automation tools, written in Rust.β36Feb 23, 2026Updated last week
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.β108Feb 11, 2026Updated 3 weeks ago
- β19Jul 12, 2024Updated last year
- β25Dec 4, 2025Updated 3 months ago
- Open-source AI acceleration on FPGA: from ONNX to RTLβ49Jan 5, 2026Updated 2 months ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.β18Feb 3, 2026Updated last month
- Modern GTKWave alternativeβ36Feb 8, 2026Updated 3 weeks ago
- A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spadβ¦β47Feb 24, 2026Updated last week
- An open-source Simulation Trace Format specificationβ15Nov 12, 2025Updated 3 months ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.β15Nov 19, 2024Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulusβ117Apr 1, 2024Updated last year
- End-to-end synthesis and P&R toolchainβ94Feb 20, 2026Updated 2 weeks ago
- design and verification of asynchronous circuitsβ43Feb 27, 2026Updated last week
- Veryl: A Modern Hardware Description Languageβ893Updated this week
- β28Mar 31, 2025Updated 11 months ago
- VS Code based debugger for hardware designs in Amaranth or Verilogβ39Dec 3, 2024Updated last year
- A Hardware Description Language based on the Rust Programming Languageβ288Updated this week
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level codeβ¦β58Oct 27, 2024Updated last year
- β21Feb 20, 2026Updated 2 weeks ago
- β19Jan 2, 2026Updated 2 months ago
- Fearless hardware designβ198Aug 20, 2025Updated 6 months ago
- LL(k) and LALR(1) parser generator for Rustβ233Feb 26, 2026Updated last week
- Re-coded Gowin GW1N primitives for Verilator useβ21Aug 19, 2022Updated 3 years ago
- A new Hardware Design Language that keeps you in the driver's seatβ124Updated this week
- Analyze experimental data with Programming by Navigationβ17Feb 24, 2026Updated last week
- The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming languagβ¦β471Jan 18, 2026Updated last month
- high-performance RTL simulatorβ186Jun 19, 2024Updated last year
- A Just-In-Time Compiler for Verilog from VMware Researchβ24Dec 14, 2020Updated 5 years ago
- Code repository for Coppelia toolβ23Nov 12, 2020Updated 5 years ago
- β30Oct 19, 2025Updated 4 months ago
- A fork of Yosys that integrates the CellIFT passβ13Jul 23, 2025Updated 7 months ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at onceβ13Mar 27, 2025Updated 11 months ago
- RTLMeter benchmark suiteβ29Feb 24, 2026Updated last week
- Logic circuit analysis and optimizationβ45Feb 2, 2026Updated last month
- β22Feb 25, 2026Updated last week
- LEC - Logic Equivalence Checking - Formal Verificationβ33Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017β463Nov 4, 2025Updated 4 months ago
- Rust Test Bench - write HDL tests in Rust.β24Nov 28, 2022Updated 3 years ago