ethanuppal / marlinLinks
🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl
☆65Updated last month
Alternatives and similar repositories for marlin
Users that are interested in marlin are comparing it to the libraries listed below
Sorting:
- Verilator Porcelain☆49Updated last year
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆89Updated last month
- Read and write VCD (Value Change Dump) files in Rust☆44Updated last year
- A Hardware Description Language that doesn't make you want to pull your hair out | read-only mirror of https://gitlab.com/spade-lang/spad…☆31Updated last week
- Logic circuit analysis and optimization☆42Updated last month
- An HDL embedded in Rust.☆200Updated last year
- A hardware compiler based on LLHD and CIRCT☆262Updated 3 months ago
- The LLHD reference simulator.☆39Updated 5 years ago
- 21st century electronic design automation tools, written in Rust.☆31Updated last week
- ☆14Updated this week
- A Hardware Description Language based on the Rust Programming Language☆242Updated last week
- Fearless hardware design☆181Updated last month
- End-to-end synthesis and P&R toolchain☆89Updated 2 weeks ago
- A new Hardware Design Language that keeps you in the driver's seat☆116Updated this week
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- A simple digital waveform viewer with vi-like key bindings.☆141Updated 6 months ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆48Updated 9 months ago
- A SystemVerilog language server based on the Slang parser and library.☆36Updated last week
- RISCV Core written in Calyx☆17Updated last year
- ☆30Updated 2 years ago
- A SystemVerilog Language Server☆184Updated 6 months ago
- Native Rust implementation of the FST waveform format from GTKWave.☆13Updated last month
- Rust Test Bench - write HDL tests in Rust.☆23Updated 2 years ago
- RISC-V out-of-order core for education and research purposes☆63Updated last week
- A dependency management tool for hardware projects.☆323Updated this week
- A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding☆22Updated 7 months ago
- Low Level Hardware Description — A foundation for building hardware design tools.☆421Updated 3 years ago
- SystemVerilog linter☆359Updated 3 weeks ago
- Verilog AST☆21Updated last year
- ☆30Updated 2 weeks ago