cornell-zhang / facedetect-fpga
☆45Updated 5 years ago
Alternatives and similar repositories for facedetect-fpga:
Users that are interested in facedetect-fpga are comparing it to the libraries listed below
- This repo is for ECE44x (Fall2015-Spring2016)☆19Updated 7 years ago
- ☆83Updated 4 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 7 years ago
- ☆19Updated 7 years ago
- verilog CNN generator for FPGA☆34Updated 4 years ago
- Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.☆54Updated 7 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- ☆39Updated 7 years ago
- Xilinx Deep Learning IP☆91Updated 3 years ago
- Caffe to VHDL☆67Updated 4 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- ☆57Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆41Updated last month
- MAERI public release☆31Updated 3 years ago
- The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track☆89Updated 6 years ago
- ☆14Updated 5 years ago
- Systolic-array based Deep Learning Accelerator generator☆24Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- Verilog library for implementing neural networks.☆26Updated 10 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆31Updated 5 years ago
- OpenCL Labs for PAPAA Summer School 2016 Edition☆46Updated 7 years ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 6 years ago
- MAESTRO binary release☆22Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆57Updated 3 years ago
- ☆70Updated 5 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆25Updated 4 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆40Updated 3 years ago