chili-chips-ba / wireguard-fpgaView external linksLinks
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
☆1,299Jan 27, 2026Updated 3 weeks ago
Alternatives and similar repositories for wireguard-fpga
Users that are interested in wireguard-fpga are comparing it to the libraries listed below
Sorting:
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated 6 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆36Feb 23, 2025Updated 11 months ago
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆22Updated this week
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆76Dec 30, 2025Updated last month
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆88Oct 16, 2025Updated 4 months ago
- Master-thesis-final☆19Oct 9, 2023Updated 2 years ago
- The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With sta…☆57Updated this week
- A Rocket-Chip with a Dynamically Randomized LLC☆13Sep 18, 2024Updated last year
- LM32 processor module for Ghidra. Useful for AMD SMU reverse engineering.☆14Dec 7, 2025Updated 2 months ago
- The open-source Zynq 7000 BSP generator for openXC7☆53Jan 21, 2025Updated last year
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource…☆55Updated this week
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆30Mar 29, 2013Updated 12 years ago
- UART to AXI Stream interface written in VHDL☆18Oct 20, 2022Updated 3 years ago
- BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard☆61Aug 21, 2023Updated 2 years ago
- RV32I by cats☆15Sep 4, 2023Updated 2 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆59Nov 14, 2025Updated 3 months ago
- Open-source RTL logic simulator with CUDA acceleration☆256Sep 30, 2025Updated 4 months ago
- SpiceBind – spice inside HDL simulator