Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
☆1,329May 3, 2026Updated this week
Alternatives and similar repositories for wireguard-fpga
Users that are interested in wireguard-fpga are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆37Feb 23, 2025Updated last year
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆84Updated this week
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated 9 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆96Updated this week
- The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With sta…☆72Updated this week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Master-thesis-final☆19Oct 9, 2023Updated 2 years ago
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource…☆67Updated this week
- RV32I by cats☆15Sep 4, 2023Updated 2 years ago
- The open-source Zynq 7000 BSP generator for openXC7☆56Jan 21, 2025Updated last year
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆33Oct 15, 2024Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆61Nov 14, 2025Updated 5 months ago
- Open Logic FPGA Standard Library☆915Apr 29, 2026Updated last week
- BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard☆64Aug 21, 2023Updated 2 years ago
- ECP5 FPGA DEV BOARD☆10Apr 19, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities☆147Mar 6, 2026Updated 2 months ago
- assorted library of utility cores for amaranth HDL☆105Sep 17, 2024Updated last year
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆26Mar 5, 2025Updated last year
- Open-source RTL logic simulator with CUDA acceleration☆273Sep 30, 2025Updated 7 months ago
- A Rocket-Chip with a Dynamically Randomized LLC☆13Sep 18, 2024Updated last year
- Example designs for using Ethernet FMC without a processor (ie. state machine based)☆35Apr 9, 2026Updated last month
- LM32 processor module for Ghidra. Useful for AMD SMU reverse engineering.☆17Dec 7, 2025Updated 5 months ago
- SGMII☆14Jul 17, 2014Updated 11 years ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆53Apr 22, 2026Updated 2 weeks ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- RISC-V-based many-core neuromorphic architecture☆16Apr 13, 2026Updated 3 weeks ago
- sump3 logic analyzer☆42Feb 2, 2026Updated 3 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆73Feb 12, 2026Updated 2 months ago
- micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop☆22Feb 25, 2025Updated last year
- LiteX development baseboards arround the SQRL Acorn.☆74Apr 22, 2026Updated 2 weeks ago
- Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)☆15Apr 14, 2026Updated 3 weeks ago
- UART to AXI Stream interface written in VHDL☆18Oct 20, 2022Updated 3 years ago
- Linux porting to NonTrivialMIPS (based on linux-stable)☆12Aug 17, 2019Updated 6 years ago
- Opensource DDR3 Controller☆430Jan 18, 2026Updated 3 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- An open-source HDL register code generator fast enough to run in real time.☆88Apr 27, 2026Updated last week
- Project Peppercorn GateMate Test Cases☆16Feb 25, 2026Updated 2 months ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆29Mar 29, 2013Updated 13 years ago
- RP2040 firmware for controlling GPIO over USB CDC with AT commands☆14Dec 22, 2024Updated last year
- Fixed-point math library with VHDL, Python and MATLAB support☆39Apr 13, 2026Updated 3 weeks ago
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆100Mar 23, 2026Updated last month
- A Python package for generating HDL wrappers and top modules for HDL sources☆73Updated this week