chili-chips-ba / wireguard-fpga
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
☆80Updated this week
Alternatives and similar repositories for wireguard-fpga:
Users that are interested in wireguard-fpga are comparing it to the libraries listed below
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆61Updated this week
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆167Updated last year
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- Naive Educational RISC V processor☆83Updated 6 months ago
- DisplayPort IP-core☆63Updated last week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆98Updated last month
- System on Chip toolkit for Amaranth HDL☆88Updated 6 months ago
- Nix flake for openXC7☆36Updated last month
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆76Updated 3 years ago
- Board definitions for Amaranth HDL☆114Updated last month
- Experimental flows using nextpnr for Xilinx devices☆234Updated 6 months ago
- Small footprint and configurable SPI core☆41Updated 2 weeks ago
- Experimental flows using nextpnr for Xilinx devices☆44Updated last week
- An FPGA reverse engineering and documentation project☆43Updated this week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆91Updated 8 months ago
- Building and deploying container images for open source electronic design automation (EDA)☆114Updated 7 months ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆54Updated 2 years ago
- PicoRV☆44Updated 5 years ago
- Use an MPSSE FTDI device as a JTAG interface in Quartus tools☆20Updated last year
- ☆45Updated 3 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆117Updated 5 months ago
- Small footprint and configurable Inter-Chip communication cores☆57Updated 2 weeks ago
- CoreScore☆151Updated 3 months ago
- BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard☆47Updated last year
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆72Updated 10 months ago
- Project X-Ray Database: XC7 Series☆67Updated 3 years ago
- ☆50Updated 2 years ago
- Bitstream relocation and manipulation tool.☆44Updated 2 years ago
- 64-bit multicore Linux-capable RISC-V processor☆91Updated last week
- PCIe analyzer experiments☆52Updated 4 years ago