fcayci / vhdl-axis-uart
UART to AXI Stream interface written in VHDL
☆16Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for vhdl-axis-uart
- JESD204b modules in VHDL☆29Updated 5 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated 3 months ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆22Updated 4 months ago
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆30Updated 2 months ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆12Updated 6 years ago
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆42Updated 2 years ago
- I2C Slave Interface (Vhdl)☆20Updated 2 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆27Updated 3 years ago
- development interface mil-std-1553b for system on chip☆19Updated 6 years ago
- Slides and lab instructions for the mastering MicroBlaze session☆33Updated 2 years ago
- A testbench for an axi lite custom IP☆22Updated 9 years ago
- A collection of Opal Kelly provided design resources☆15Updated last month
- ☆32Updated last year
- File editor for the Xilinx AXI Traffic Generator IP☆15Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆43Updated 11 months ago
- Small footprint and configurable JESD204B core☆40Updated last month
- The implementation of AD9371 on KC705☆20Updated 4 years ago
- VHDL PCIe Transceiver☆26Updated 4 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆16Updated 7 months ago
- DPLL for phase-locking to 1PPS signal☆28Updated 8 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆43Updated 2 years ago
- ☆20Updated 2 weeks ago
- This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…☆64Updated 7 years ago
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆19Updated 8 years ago
- Sata 2 Host Controller for FPGA implementation☆13Updated 7 years ago
- Verilog Repository for GIT☆29Updated 3 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆50Updated 3 years ago
- VHDL Library for implementing common DSP functionality.☆27Updated 6 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆55Updated 2 years ago