UART to AXI Stream interface written in VHDL
☆18Oct 20, 2022Updated 3 years ago
Alternatives and similar repositories for vhdl-axis-uart
Users that are interested in vhdl-axis-uart are comparing it to the libraries listed below
Sorting:
- Repository containing the DSP gateware cores☆14Feb 6, 2026Updated 3 weeks ago
- DSSS Wireless transmit-receive system in VHDL☆14Dec 19, 2017Updated 8 years ago
- JESD204b modules in VHDL☆30Apr 18, 2019Updated 6 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 5 years ago
- This repository consists of the processing of the recieved GPS signals at the receiver side. MATLAB has been put to use. MATLAB to HDL ma…☆18Jul 12, 2017Updated 8 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary t…☆13Oct 8, 2020Updated 5 years ago
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆16Dec 6, 2020Updated 5 years ago
- ☆18Sep 16, 2020Updated 5 years ago
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 7 years ago
- ☆47Feb 18, 2026Updated 2 weeks ago
- Synthesizable FIR filters in VHDL☆14Jul 19, 2019Updated 6 years ago
- PS/2 Keyboard IP written in VHDL for Xilinx FPGA☆17Jul 11, 2015Updated 10 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 7 years ago
- Prototype phase noise analyzer☆21Nov 28, 2020Updated 5 years ago
- The implementation of AD9371 on KC705☆20Jun 10, 2025Updated 8 months ago
- Sample minimal Vivado project for Parallella FPGA☆45May 15, 2016Updated 9 years ago
- ☆24Apr 12, 2025Updated 10 months ago
- VHDL functional blocks with their simulations and test sequences☆20Updated this week
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 4 years ago
- ☆25Jun 26, 2014Updated 11 years ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 3 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆33May 17, 2020Updated 5 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆18Oct 23, 2019Updated 6 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆37Oct 15, 2025Updated 4 months ago
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆29Dec 1, 2016Updated 9 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆27Jul 11, 2024Updated last year
- Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1☆39Feb 18, 2024Updated 2 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 9 years ago
- VHDL Library for implementing common DSP functionality.☆31Oct 5, 2018Updated 7 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Jun 8, 2017Updated 8 years ago
- VHDL PCIe Transceiver☆32Jul 2, 2020Updated 5 years ago
- Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!☆25Oct 19, 2016Updated 9 years ago
- EPICS Channel Access for node.js☆19Oct 13, 2020Updated 5 years ago
- Useful set of library functions for VHDL☆47Nov 24, 2013Updated 12 years ago
- VHDL codes to generate GPS L1 C/A and Galileo E1OS and E5 PRNs and dataless signals. Secondary codes not included.☆32Feb 22, 2019Updated 7 years ago