fcayci / vhdl-axis-uart
UART to AXI Stream interface written in VHDL
☆16Updated 2 years ago
Alternatives and similar repositories for vhdl-axis-uart:
Users that are interested in vhdl-axis-uart are comparing it to the libraries listed below
- JESD204b modules in VHDL☆29Updated 5 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated 5 months ago
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆32Updated this week
- Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard☆42Updated 3 years ago
- Verilog IP Cores & Tests☆12Updated 6 years ago
- I2C Slave Interface (Vhdl)☆22Updated 2 years ago
- DPLL for phase-locking to 1PPS signal☆28Updated 8 years ago
- Slides and lab instructions for the mastering MicroBlaze session☆34Updated 2 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆15Updated 2 months ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆12Updated 6 years ago
- Extensible FPGA control platform☆56Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- Small footprint and configurable JESD204B core☆40Updated 3 weeks ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆47Updated 2 years ago
- The implementation of AD9371 on KC705☆20Updated 4 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆22Updated 6 months ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆42Updated 3 years ago
- VHDL PCIe Transceiver☆26Updated 4 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 12 years ago
- development interface mil-std-1553b for system on chip☆19Updated 6 years ago
- SDRAM controller for MIPSfpga+ system☆21Updated 4 years ago
- ☆32Updated last year
- A collection of Opal Kelly provided design resources☆15Updated 3 months ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆28Updated 9 months ago
- OscillatorIMP ecosystem FPGA IP sources☆26Updated last week
- VHDL Modules☆23Updated 9 years ago
- Verilog Repository for GIT☆31Updated 3 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆30Updated 3 years ago
- ☆30Updated 3 years ago