Alternatives and similar repositories for ethernet-fmc-processorless

Users that are interested in ethernet-fmc-processorless are comparing it to the libraries listed below

• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆35Updated 8 months ago
• adki / RTL-Design-For-FPGA
  Engineering Program on RTL Design for FPGA Accelerator
  ☆31Updated 5 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆70Updated 6 months ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆68Updated 2 months ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 3 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆62Updated this week
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆80Updated 3 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 2 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆41Updated last month
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆55Updated 5 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆51Updated last year
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆95Updated 5 years ago
• CospanDesign / python-pci
  Python interface to PCIE
  ☆40Updated 7 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆125Updated 2 weeks ago
• antmicro / nvme-verilog-pcie
  ☆79Updated 3 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆75Updated 2 years ago
• DUNE / pl-nvme
  ☆36Updated 5 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆17Updated 5 years ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆38Updated 10 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated last year
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆66Updated this week
• verilator / example-systemverilog
  ☆40Updated last year
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆71Updated 2 months ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 9 months ago