Alternatives and similar repositories for BrightAI-Blackwire

Users that are interested in BrightAI-Blackwire are comparing it to the libraries listed below

• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆33Updated 3 weeks ago
• colognechip / gatemate_ila
  The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …
  ☆51Updated last week
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆63Updated last week
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 6 months ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated 2 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆68Updated 9 months ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆46Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆71Updated last year
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆68Updated this week
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆55Updated this week
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆28Updated 4 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 3 years ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 2 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆60Updated last week
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆46Updated 6 months ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆29Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated last month
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆47Updated 7 months ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆64Updated last week
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated 7 months ago