FPGA-House-AG / BrightAI-Blackwire
BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard
☆46Updated last year
Alternatives and similar repositories for BrightAI-Blackwire:
Users that are interested in BrightAI-Blackwire are comparing it to the libraries listed below
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 4 months ago
- FuseSoC standard core library☆125Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆65Updated 9 months ago
- ☆59Updated 3 years ago
- ☆41Updated 4 years ago
- FPGA reference design for the the Swerv EH1 Core☆69Updated 5 years ago
- RISC-V Nox core☆62Updated 6 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 8 months ago
- Bitstream relocation and manipulation tool.☆43Updated 2 years ago
- Announcements related to Verilator☆38Updated 4 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆110Updated last year
- Extensible FPGA control platform☆56Updated last year
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments☆51Updated last month
- Open-source high performance AXI4-based HyperRAM memory controller☆61Updated 2 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆49Updated 2 weeks ago
- Spen's Official OpenOCD Mirror☆48Updated 10 months ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 2 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆113Updated 2 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated this week
- Naive Educational RISC V processor☆77Updated 3 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆49Updated this week
- Experimental flows using nextpnr for Xilinx devices☆41Updated last month
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆82Updated 3 years ago
- The multi-core cluster of a PULP system.☆68Updated last week
- FPGA tool performance profiling☆102Updated 11 months ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆73Updated this week
- FPGA250 aboard the eFabless Caravel☆27Updated 4 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆80Updated 8 months ago
- ☆76Updated 10 months ago