A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.
☆81Dec 30, 2025Updated 3 months ago
Alternatives and similar repositories for openeye-CamSI
Users that are interested in openeye-CamSI are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆37Feb 23, 2025Updated last year
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆22Updated this week
- Master-thesis-final☆19Oct 9, 2023Updated 2 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆95Feb 26, 2026Updated last month
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated 8 months ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆32May 15, 2023Updated 2 years ago
- The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With sta…☆66Apr 6, 2026Updated last week
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource…☆64Updated this week
- Simple extension boards for Olimex GateMate FPGA Board☆20Jun 30, 2025Updated 9 months ago
- Artix7 SOM☆19Sep 9, 2024Updated last year
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated last year
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆72Feb 12, 2026Updated 2 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆61Nov 14, 2025Updated 5 months ago
- Episode I - RISCV CPU implementation tutorial for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆17Apr 7, 2026Updated last week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆28Feb 2, 2026Updated 2 months ago
- HDL and C source for WAVE Zynq Ultrascale+ SoC☆19Nov 16, 2021Updated 4 years ago
- FPGA digital camera controller and frame capture device in VHDL☆15Feb 11, 2013Updated 13 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆22Apr 4, 2026Updated 2 weeks ago
- ☆15Dec 1, 2022Updated 3 years ago
- Some assorted examples of nmigen designs☆19Nov 5, 2023Updated 2 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- Resources for my first book☆23Jun 21, 2023Updated 2 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆38Oct 25, 2020Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- ☆21Sep 26, 2025Updated 6 months ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆78Apr 6, 2026Updated last week
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆20Jul 22, 2024Updated last year
- assorted library of utility cores for amaranth HDL☆103Sep 17, 2024Updated last year
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆26Jan 28, 2025Updated last year
- ☆42Mar 9, 2026Updated last month
- Project Peppercorn GateMate Test Cases☆15Feb 25, 2026Updated last month
- ☆29Dec 15, 2025Updated 4 months ago
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆19Jul 28, 2025Updated 8 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Fixed-point math library with VHDL, Python and MATLAB support☆39Oct 15, 2025Updated 6 months ago
- Snapshot of the April 2000 XSOC/xr16 Project Beta 0.93, collateral for Jan Gray's series "Building a RISC System in an FPGA" published in…☆13Jan 7, 2023Updated 3 years ago
- ☆24Nov 11, 2025Updated 5 months ago
- FPGA based WiFi Intrusion detection system☆35Jan 4, 2026Updated 3 months ago
- BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard☆64Aug 21, 2023Updated 2 years ago
- Another world port ESP32 TTGO VGA32 v1.4☆13Sep 23, 2024Updated last year
- This repo will show how to build FFTW on Zynq☆18Jan 31, 2025Updated last year