chili-chips-ba / openeye-CamSIView external linksLinks
A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.
☆76Dec 30, 2025Updated last month
Alternatives and similar repositories for openeye-CamSI
Users that are interested in openeye-CamSI are comparing it to the libraries listed below
Sorting:
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆36Feb 23, 2025Updated 11 months ago
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆22Updated this week
- Master-thesis-final☆19Oct 9, 2023Updated 2 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆88Oct 16, 2025Updated 4 months ago
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated 6 months ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆32May 15, 2023Updated 2 years ago
- Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek sec…☆1,299Jan 27, 2026Updated 3 weeks ago
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated 9 months ago
- Artix7 SOM☆18Sep 9, 2024Updated last year
- The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With sta…☆57Updated this week
- Snapshot of the April 2000 XSOC/xr16 Project Beta 0.93, collateral for Jan Gray's series "Building a RISC System in an FPGA" published in…☆12Jan 7, 2023Updated 3 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆27Feb 2, 2026Updated 2 weeks ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆70Updated this week
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆15Updated this week
- ☆31Jan 22, 2026Updated 3 weeks ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- Another world port ESP32 TTGO VGA32 v1.4☆13Sep 23, 2024Updated last year
- FPGA digital camera controller and frame capture device in VHDL☆15Feb 11, 2013Updated 13 years ago
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆18Jul 28, 2025Updated 6 months ago
- ERASynth Micro Documentation☆15Nov 21, 2019Updated 6 years ago
- An embeddable FPGA SoM designed for high-speed audio and USB applications.☆24Mar 15, 2025Updated 11 months ago
- Simple extension boards for Olimex GateMate FPGA Board☆18Jun 30, 2025Updated 7 months ago
- ☆21Sep 26, 2025Updated 4 months ago
- FPGA for uSDR☆20Dec 19, 2025Updated last month
- ☆15Dec 1, 2022Updated 3 years ago
- ☆15May 17, 2025Updated 9 months ago
- Resources for my first book☆22Jun 21, 2023Updated 2 years ago
- FPGA based WiFi Intrusion detection system☆36Jan 4, 2026Updated last month
- Simple UVM testbench development using the uvmtb_template files☆22Jan 16, 2025Updated last year
- VexRiscV system with GDB-Server in Hardware☆21Jul 5, 2023Updated 2 years ago
- ☆18Nov 11, 2025Updated 3 months ago
- Some assorted examples of nmigen designs☆19Nov 5, 2023Updated 2 years ago
- USB DFU bootloader gateware / firmware for FPGAs☆70Jan 30, 2026Updated 2 weeks ago
- ERASynth Micro Arduino Firmware☆16Dec 10, 2020Updated 5 years ago
- FPGA implementation of the AnotherWorld CPU (equivalent to the original VM)☆16Apr 6, 2020Updated 5 years ago
- L5 R5:Espressif 400MHz RISC-V MCU (ESP32-P4)☆16Jan 10, 2023Updated 3 years ago
- Control application for NWT network analyzers☆19Nov 9, 2020Updated 5 years ago
- Python package for working with Keysight/Agilent/HP test equipment.☆18Dec 5, 2024Updated last year
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆20Jul 22, 2024Updated last year