chili-chips-ba / uberClockLinks
Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numerical sauce. The best of all is that the sauce is not secret, but fully open to the public.
☆17Updated 3 weeks ago
Alternatives and similar repositories for uberClock
Users that are interested in uberClock are comparing it to the libraries listed below
Sorting:
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆33Updated 9 months ago
- assorted library of utility cores for amaranth HDL☆97Updated last year
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆81Updated last month
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆70Updated last week
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆40Updated last week
- VHDL Library for implementing common DSP functionality.☆30Updated 7 years ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 7 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆39Updated last week
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆71Updated 4 years ago
- Efabless mpw7 submission☆13Updated last year
- ☆27Updated 7 months ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆30Updated 10 months ago
- A tiny example of PCM to PDM pipeline on FPGA☆22Updated 3 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆57Updated last week
- a USB2 highspeed device core, written in amaranth HDL☆52Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆76Updated 3 weeks ago
- ☆30Updated 4 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- Library of reusable VHDL components☆28Updated last year
- SpiceBind – spice inside HDL simulator☆56Updated 4 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated this week
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆25Updated last year
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆76Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆26Updated last month
- A compact, configurable RISC-V core☆12Updated 3 months ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆30Updated last week