chili-chips-ba / uberClockLinks
Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numerical sauce. The best of all is that the sauce is not secret, but fully open to the public.
☆12Updated 2 weeks ago
Alternatives and similar repositories for uberClock
Users that are interested in uberClock are comparing it to the libraries listed below
Sorting:
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆29Updated 7 months ago
- assorted library of utility cores for amaranth HDL☆96Updated last year
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆74Updated this week
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆64Updated 2 months ago
- VHDL Library for implementing common DSP functionality.☆30Updated 7 years ago
- ☆26Updated 6 months ago
- Generate Zynq configurations without using the vendor GUI☆30Updated 2 years ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆29Updated 8 months ago
- Demo projects for various Kintex FPGA boards☆62Updated 4 months ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 6 months ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆74Updated 3 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- An open-source HDL register code generator fast enough to run in real time.☆73Updated 3 weeks ago
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes... now for the first time in opensour…☆17Updated last month
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆71Updated 4 years ago
- Experimental flows using nextpnr for Xilinx devices☆50Updated 4 months ago
- The first-ever opensource RTL stack for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With sta…☆22Updated this week
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆26Updated last week
- A Python package for generating HDL wrappers and top modules for HDL sources☆36Updated last week
- Convenience script to install the nextpnr-xilinx toolchain for Kintex7, Artix7, Spartan7 and Zynq7☆90Updated 3 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆54Updated 2 weeks ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated this week
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆120Updated 4 years ago
- a USB2 highspeed device core, written in amaranth HDL☆52Updated last year
- SpiceBind – spice inside HDL simulator☆55Updated 3 months ago
- ☆46Updated 2 years ago
- Digital Signal Processing and Well-Known Modulations on HDL☆41Updated 4 months ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 3 years ago
- Use amaranth-to-litex to simply import Amaranth code into a Litex project.☆15Updated last year
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆107Updated last month