chili-chips-ba / uberClockLinks
Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numerical sauce. The best of all is that the sauce is not secret, but fully open to the public.
☆11Updated 2 weeks ago
Alternatives and similar repositories for uberClock
Users that are interested in uberClock are comparing it to the libraries listed below
Sorting:
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆28Updated 5 months ago
- assorted library of utility cores for amaranth HDL☆94Updated 10 months ago
- Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 4 months ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆72Updated 3 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …☆13Updated this week
- VHDL Library for implementing common DSP functionality.☆30Updated 6 years ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆71Updated 3 years ago
- ☆29Updated 4 years ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆23Updated 3 weeks ago
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆57Updated 3 weeks ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆66Updated last week
- ☆23Updated 3 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆63Updated 3 weeks ago
- LiteX based FPGA gateware for Thunderscope.☆23Updated last month
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆116Updated 4 years ago
- SAR ADC on tiny tapeout☆42Updated 6 months ago
- a USB2 highspeed device core, written in amaranth HDL☆50Updated 10 months ago
- Projects published on controlpaths.com and hackster.io☆41Updated 3 years ago
- A tiny example of PCM to PDM pipeline on FPGA☆21Updated 3 years ago
- sliding DFT for FPGA, targetting Lattice ICE40 1k☆77Updated 5 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Updated last year
- ☆45Updated 2 years ago
- Time to Digital Converter (TDC)☆31Updated 4 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆23Updated last year
- Digital Signal Processing and Well-Known Modulations on HDL☆41Updated 2 months ago
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆109Updated 8 years ago
- Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1☆33Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆35Updated this week
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆59Updated 4 years ago