srimanthtenneti / SOC-Design-ARM-M0
This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.
☆11Updated last year
Alternatives and similar repositories for SOC-Design-ARM-M0:
Users that are interested in SOC-Design-ARM-M0 are comparing it to the libraries listed below
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆26Updated 3 years ago
- ☆16Updated 6 years ago
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆18Updated last year
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆24Updated 2 months ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 2 months ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆32Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆37Updated 3 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆19Updated 5 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using h…☆15Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆23Updated 6 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 3 months ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆17Updated 8 months ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆14Updated 2 years ago
- USB 1.1 Host and Function IP core☆21Updated 10 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆30Updated last year
- USB -> AXI Debug Bridge☆36Updated 3 years ago
- Verilog CAN controller that is compatible to the SJA 1000.☆12Updated 4 years ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆23Updated 10 months ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 4 months ago
- ☆12Updated last year
- This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online I…☆19Updated 4 years ago