This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.
☆12Sep 6, 2023Updated 2 years ago
Alternatives and similar repositories for SOC-Design-ARM-M0
Users that are interested in SOC-Design-ARM-M0 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆21May 24, 2023Updated 3 years ago
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆24Nov 17, 2021Updated 4 years ago
- An bare metal STM32F303CB project that generates a perfect 1KHz sine wave and 4 90 degree phase shifted square waves at also 1KHz☆18Mar 26, 2021Updated 5 years ago
- practice configure AHB-Lite bus protocol☆20Mar 11, 2019Updated 7 years ago
- DIY Jlink V9 debugger☆33Dec 29, 2020Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Cortex_m0软核源码，可以在FPGA上直接跑，包含UART、定时器这些外设，可以用keil写用户代码。可以看看《Cortex-M0 全可编程SoC原理及实现》这本书☆27Mar 15, 2021Updated 5 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆13Mar 22, 2021Updated 5 years ago
- ☆13Nov 13, 2022Updated 3 years ago
- Synthesizable SystemVerilog IP-Core of the I2S Receiver☆10Jun 7, 2020Updated 6 years ago
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 4 years ago
- Design and simulate a simplified ARM single-cycle processor using SystemVerilog.☆10Sep 13, 2019Updated 6 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆34Jul 4, 2024Updated 2 years ago
- Parametric Binary to BCD Converter Using Double Dabble / Shift and Add 3 Algorithm☆16May 28, 2015Updated 11 years ago
- ☆20Jun 18, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- EBAZ4205 is Xilinx Zynq based mining board used in Ebang Ebit E9+ bitcoin miner machine.☆10Jan 18, 2022Updated 4 years ago
- Debug waveforms with GDB☆33Nov 12, 2025Updated 8 months ago
- LSTM neural network (verilog)☆16Dec 5, 2018Updated 7 years ago
- A set of small Verilog projects, to simulate and implement on FPGA development boards☆15Mar 5, 2018Updated 8 years ago
- ☆17Sep 28, 2017Updated 8 years ago
- Parallel implementation of Smith–Waterman using OpenMP☆10Oct 28, 2020Updated 5 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- 微信小程序报名工具讲座脚本,不会python的同学也能抢!☆16Dec 29, 2023Updated 2 years ago
- 单周期CPU设计与实现☆15Dec 30, 2022Updated 3 years ago
- Parameterized Booth Multiplier in Verilog 2001☆51Oct 30, 2022Updated 3 years ago
- ☆11Sep 9, 2022Updated 3 years ago
- ☆13Mar 10, 2023Updated 3 years ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instr…☆12Jan 24, 2022Updated 4 years ago
- ☆10Nov 4, 2022Updated 3 years ago
- HDL components to build a customized Wishbone crossbar switch☆15May 30, 2019Updated 7 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆39Jul 23, 2023Updated 3 years ago
- risc-v 单周期和流水线cpu设计， 基于miniRV-1指令集，语言verilog☆11Feb 23, 2023Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆56Jan 4, 2022Updated 4 years ago
- IC Verification & SV Demo☆60Sep 29, 2021Updated 4 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu☆14Updated this week
- Hardware Formal Verification☆17Aug 10, 2020Updated 5 years ago
- AXI Interconnect☆58Aug 20, 2021Updated 4 years ago