☆13Nov 13, 2022Updated 3 years ago
Alternatives and similar repositories for spi
Users that are interested in spi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆10Nov 4, 2022Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Mar 17, 2022Updated 4 years ago
- Cortex_m0软核源码,可以在FPGA上直接跑,包含UART、定时器这些外设,可以用keil写用户代码。可以看看《Cortex-M0 全可编程SoC原理及实现》这本书☆26Mar 15, 2021Updated 5 years ago
- Hardware implementation, using a Digilent Basys-3 FPGA board, of the computer described in J. Clark Scott's book "But How Do It Know?".☆15Aug 3, 2020Updated 5 years ago
- Verilog ADC interface for adc128s022 found in De0 Nano☆15Jul 7, 2015Updated 10 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆76Aug 30, 2022Updated 3 years ago
- ☆12Jun 18, 2020Updated 5 years ago
- Implementation of PSO Algorithm to Optimize SVM☆11May 18, 2019Updated 7 years ago
- Learning Machine Learning with TensorFlow☆10Feb 20, 2017Updated 9 years ago
- ☆15Aug 10, 2023Updated 2 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 5 years ago
- This repo features a Verilog-based PID controller optimized for real-time ASIC and FPGA applications. It includes a testbench for linear …☆33Oct 26, 2023Updated 2 years ago
- Basic Verilog modules☆13Jul 8, 2021Updated 4 years ago
- This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.☆12Sep 6, 2023Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- 51单片机的1602时钟、具有闹钟等功能☆10Jan 3, 2025Updated last year
- General Purpose IO with APB4 interface☆16May 10, 2024Updated 2 years ago
- ☆22Sep 26, 2025Updated 8 months ago
- ☆13Jan 9, 2023Updated 3 years ago
- A convolutional autoencoder for feature extraction, with an SVM for image classification.☆10Jan 30, 2019Updated 7 years ago
- Small and simple, primitive SoC with GPU, CPU, RAM, GPIO☆14Dec 29, 2016Updated 9 years ago
- 卷积神经网络提取特征并用于SVM//www.cnblogs.com/chuxiuhong/p/6132814.html☆16May 10, 2018Updated 8 years ago
- ☆34Jul 9, 2025Updated 11 months ago
- risc-v 单周期和流水线cpu设计, 基于miniRV-1指令集,语言verilog☆11Feb 23, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Enhanced 6502/65C02 Microprogrammed FPGA Processor Core (Verilog-2001)☆34Mar 15, 2022Updated 4 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- 使用LDA+SVM进行文本的分类☆22Jul 23, 2017Updated 8 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- ☆12Mar 10, 2023Updated 3 years ago
- Design and simulate a simplified ARM single-cycle processor using SystemVerilog.☆10Sep 13, 2019Updated 6 years ago
- HDL components to build a customized Wishbone crossbar switch☆15May 30, 2019Updated 7 years ago
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆19May 28, 2021Updated 5 years ago
- Hardware Formal Verification☆17Aug 10, 2020Updated 5 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆16Dec 3, 2022Updated 3 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆18Oct 6, 2024Updated last year
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆16Oct 21, 2020Updated 5 years ago
- RiscSoC 是一个芯片集成项目,包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成,部分 SoC 使用的自己设计的内核☆13Apr 26, 2022Updated 4 years ago
- ☆20Aug 22, 2022Updated 3 years ago
- 记录一下夏季学期计算机设计与实践课上写的RISC-V单周期CPU和RISC-V五级流水线CPU☆14Sep 7, 2021Updated 4 years ago
- 单周期CPU设计与实现☆15Dec 30, 2022Updated 3 years ago