Alternatives and similar repositories for litesata_axiom

Users that are interested in litesata_axiom are comparing it to the libraries listed below

• buttercutter / noc
  A simple spidergon network-on-chip with wormhole switching feature
  ☆12Updated 4 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆68Updated 2 months ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆47Updated 3 months ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆13Updated 3 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆39Updated last week
• chili-chips-ba / openCologne-PCIE
  The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…
  ☆40Updated last week
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 6 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆48Updated 5 years ago
• plex1 / SpinalDev
  Docker Development Environment for SpinalHDL
  ☆20Updated last year
• hdlguy / vivado_tcl
  demo project to show how to use vivado tcl scripts to do everything.
  ☆17Updated 10 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆32Updated last year
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• bobbl / rudolv
  RISC-V processor
  ☆32Updated 3 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆33Updated last year
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆20Updated 2 weeks ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆49Updated 2 years ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆17Updated 6 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆31Updated 3 years ago
• xobs / coriolis
  An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.
  ☆10Updated 7 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆20Updated 4 years ago