This repo contain the PY-UVM Framework for different RISC-V Cores
☆33Sep 16, 2023Updated 3 years ago
Alternatives and similar repositories for PY_UVM_Framework
Users that are interested in PY_UVM_Framework are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Mar 17, 2023Updated 3 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 7 years ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆22Mar 22, 2023Updated 3 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆13Mar 22, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This is the base repo for our graduation project in AlexU 21☆28Jul 26, 2021Updated 5 years ago
- Solving Sudokus using open source formal verification tools☆18Aug 16, 2022Updated 4 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 7 years ago
- ☆11Apr 18, 2026Updated 6 months ago
- Many peripherals in Verilog ready to use☆41Dec 29, 2024Updated last year
- ☆182Sep 11, 2022Updated 4 years ago
- Wishbone to ARM AMBA 4 AXI☆17May 25, 2019Updated 7 years ago
- APB4 Multiplexor☆15May 10, 2024Updated 2 years ago
- A fault-injection framework using Chisel and FIRRTL☆39Sep 17, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- The UVM written in Python☆18Oct 26, 2026Updated last week
- ☆119Dec 24, 2023Updated 2 years ago
- SHA-256 cipher algorithm implementation☆13Jun 22, 2025Updated last year
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆28Jan 11, 2019Updated 7 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆18Aug 13, 2023Updated 3 years ago
- This repository contains Firmware, tools, and documentation for the Analog Paradigm Model-1 analog computer.☆11May 18, 2023Updated 3 years ago
- Verilog implementation of pipelined cpu☆13Feb 8, 2021Updated 5 years ago
- Final project for Computer Architecture FA16☆20Jan 5, 2017Updated 9 years ago
- Wishbone controller for a MEMs microphone☆16Mar 18, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- FPGA optimized RISC-V (RV32IM) implemenation☆34Nov 1, 2020Updated 6 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 6 years ago
- uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol☆21Feb 7, 2025Updated last year
- ☆12May 15, 2022Updated 4 years ago
- Memory Level Verification of Dual Port RAM using SystemVerilog and Universal Verification Methodology Environments with assertions,functi…☆30Nov 21, 2020Updated 5 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- ☆204Dec 14, 2023Updated 2 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆26Jan 1, 2022Updated 4 years ago
- Workshop that is going to be given together with the UPduino dev board☆23Oct 29, 2021Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- USB1.1 Host Controller + PHY☆18Aug 4, 2021Updated 5 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020☆27Apr 11, 2022Updated 4 years ago
- The Scale4Edge ecosystem VP☆10Aug 4, 2025Updated last year
- ☆12Jun 11, 2018Updated 8 years ago
- The Complete Vue.JS Course for Beginners - Zero to Mastery, by Packt Publishing☆15Jul 20, 2023Updated 3 years ago
- Adding UVM support to Icarus Verilog (and Verilator in near future) by taking a step-by-step, bottom-up approach.☆24Dec 27, 2022Updated 3 years ago