☆28Sep 28, 2026Updated 2 weeks ago
Alternatives and similar repositories for axi-pcie-core
Users that are interested in axi-pcie-core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 7 years ago
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆19Apr 13, 2022Updated 4 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆19Oct 23, 2019Updated 6 years ago
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 5 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A simple SystemVerilog digital phase-locked loop based (roughly) on TI's SDLA005B application note. The design includes a SystemVerilog t…☆16Aug 29, 2022Updated 4 years ago
- A Python to VHDL compiler☆18Apr 28, 2025Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆38Dec 24, 2024Updated last year
- Processor support packages☆23Feb 2, 2021Updated 5 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆14Sep 28, 2022Updated 4 years ago
- An FPGA-based NetTLP adapter☆29Mar 10, 2020Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 10 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆19Jan 25, 2022Updated 4 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆19Aug 28, 2019Updated 7 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Fixed-point math library with VHDL, Python and MATLAB support☆39Aug 12, 2026Updated 2 months ago
- XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA☆22Mar 7, 2024Updated 2 years ago
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆44Mar 5, 2026Updated 7 months ago
- ☆14Sep 14, 2017Updated 9 years ago
- SISO vector decoder for IRA-LDPC codes in VHDL☆12Oct 18, 2022Updated 4 years ago
- Hardware Snappy decompressor☆12Sep 11, 2024Updated 2 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 7 months ago
- ☆22May 5, 2022Updated 4 years ago
- An HTTP Server for FPGAs☆18Sep 26, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- ☆10Jan 15, 2023Updated 3 years ago
- Verilog PCI express components☆28Jun 26, 2023Updated 3 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆44Sep 22, 2025Updated last year
- high level VHDL floating point library for synthesis in fpga☆18Oct 8, 2026Updated last week
- FleetRec: Large-Scale Recommendation Inference on Hybrid GPU-FPGA Clusters☆16May 26, 2021Updated 5 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆41Jun 10, 2026Updated 4 months ago
- HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/☆14Dec 4, 2018Updated 7 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Networking Template Library for Vivado HLS☆30Jul 12, 2020Updated 6 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆16Dec 6, 2020Updated 5 years ago
- ☆35Jan 21, 2021Updated 5 years ago
- Virtio implementation in SystemVerilog☆50Jan 23, 2018Updated 8 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- RISC-V CSR Access Routines☆16Dec 27, 2022Updated 3 years ago