necst / xlnx-project-template
Template Repository for Xilinx HLS design flow
☆12Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for xlnx-project-template
- Image Registration on FPGAs☆19Updated 2 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆13Updated 9 months ago
- ☆23Updated 3 years ago
- Introductory examples for using PYNQ with Alveo☆48Updated last year
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆24Updated 4 years ago
- Chisel Project for Integrating RTL code into SDAccel☆17Updated 6 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- FPGA version of Rodinia in HLS C/C++☆31Updated 3 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 4 years ago
- ☆27Updated 5 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆29Updated 2 years ago
- ☆22Updated 5 years ago
- ☆8Updated last year
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- DASS HLS Compiler☆27Updated last year
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆25Updated 4 years ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆37Updated 5 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆30Updated this week
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆19Updated this week
- Accelerating SSSP for power-law graphs using an FPGA.☆21Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- ☆22Updated 3 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆40Updated last week
- ☆24Updated 5 years ago
- A SystemC + DRAMSim2 simulator for exploring the SpMV hardware accelerator design space.☆14Updated 10 years ago
- BlackParrot on Zynq☆25Updated this week
- Algorithmic C Machine Learning Library☆22Updated 3 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆59Updated 11 months ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆23Updated last month