necst / xlnx-project-templateLinks
Template Repository for Xilinx HLS design flow
☆12Updated 3 years ago
Alternatives and similar repositories for xlnx-project-template
Users that are interested in xlnx-project-template are comparing it to the libraries listed below
Sorting:
- Algorithmic C Machine Learning Library☆26Updated 10 months ago
- Image Registration on FPGAs☆21Updated 3 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆53Updated 8 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆15Updated last year
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Updated last year
- BlackParrot on Zynq☆48Updated last week
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆45Updated this week
- ☆27Updated 6 years ago
- ☆30Updated 6 years ago
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆22Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 4 years ago
- ☆13Updated 5 months ago
- Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of th…☆14Updated 5 years ago
- SoC design & prototyping☆15Updated 4 months ago
- ☆24Updated 4 years ago
- Distributed Accelerator OS☆64Updated 3 years ago
- FPGA version of Rodinia in HLS C/C++☆40Updated 4 years ago
- DASS HLS Compiler☆29Updated 2 years ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 3 months ago
- Chisel Project for Integrating RTL code into SDAccel☆17Updated 7 years ago
- DaCH: dataflow cache for high-level synthesis.☆19Updated 2 years ago
- matrix-coprocessor for RISC-V☆25Updated 6 months ago
- ☆15Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆64Updated 2 weeks ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆40Updated 6 years ago