Alternatives and similar repositories for xlnx-project-template

Users that are interested in xlnx-project-template are comparing it to the libraries listed below

• necst / iron
  Image Registration on FPGAs
  ☆21Updated 2 years ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• UCLA-VAST / hbmbench
  ☆24Updated 4 years ago
• Xilinx / SLASH
  A research shell for Alveo V80
  ☆13Updated last week
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• CGCL-codes / ScalaBFS
  A Scalable BFS Accelerator on FPGA-HBM Platform
  ☆14Updated last year
• SFU-HiAccel / uBench
  [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
  ☆31Updated 3 years ago
• template-hls / template-hls-float
  ☆29Updated 6 years ago
• necst / sdaccel_chisel_integration
  Chisel Project for Integrating RTL code into SDAccel
  ☆17Updated 7 years ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆36Updated this week
• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆47Updated 10 months ago
• SFU-HiAccel / rodinia-hls
  FPGA version of Rodinia in HLS C/C++
  ☆35Updated 4 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 3 years ago
• Xilinx / merlin-compiler
  ☆58Updated last year
• lizardll / ScalaBFS
  A Scalable BFS Accelerator on FPGA-HBM Platform
  ☆13Updated 3 years ago
• harvard-acc / ESP_Systolic_Array_Accelerator
  ☆4Updated 4 years ago
• dac-sdc / fpga_starter_2023
  ☆8Updated 2 years ago
• ECASLab / cynq
  PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.
  ☆25Updated 2 weeks ago
• enyac-group / MaxEVA
  MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine (accepted as full paper at FPT'23)
  ☆21Updated last year
• TUD-ADS / HiFlipVX
  ☆16Updated 2 years ago
• CastLab-KAIST / OpenMDS
  ☆14Updated 2 years ago
• Xilinx / pcie_qdma_ats_example
  ☆23Updated 4 years ago
• sld-columbia / hl5
  A 32-bit RISC-V Processor Designed with High-Level Synthesis
  ☆52Updated 5 years ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆23Updated 5 months ago
• sfu-arch / SpGEMM
  ☆35Updated 4 years ago
• brigio345 / DaCH
  DaCH: dataflow cache for high-level synthesis.
  ☆16Updated last year
• CMU-SAFARI / VAMPIRE
  An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …
  ☆39Updated 6 years ago
• emanueledelsozzo / awesome-fpga-programming
  An awesome curated list of languages and tools to program FPGAs
  ☆63Updated 2 years ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆46Updated 2 months ago