OscillatorIMP ecosystem FPGA IP sources
☆28Feb 22, 2026Updated 8 months ago
Alternatives and similar repositories for fpga_ip
Users that are interested in fpga_ip are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Real Digital Vivado IP Library☆10Nov 13, 2022Updated 3 years ago
- Projects for the UltraMYIR FPGA development board☆13Sep 17, 2023Updated 3 years ago
- OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing☆59Feb 22, 2026Updated 8 months ago
- IPv4/UDP stack written in VHDL code, for interfacing with an FPGA over Ethernet☆13Jun 2, 2021Updated 5 years ago
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆38Jul 10, 2019Updated 7 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Python script for generating Xilinx .coe files for RAM initializing☆20Jan 3, 2019Updated 7 years ago
- My attempt to build GPS (GNSS) receiver with a little help of gnuradio☆12Jan 6, 2024Updated 2 years ago
- ☆18Sep 2, 2020Updated 6 years ago
- Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)☆18Sep 5, 2023Updated 3 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 8 years ago
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆12Dec 20, 2013Updated 12 years ago
- Verilog network module. Models network traffic from pcap to AXI-Stream☆24Apr 24, 2021Updated 5 years ago
- Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.☆39Oct 5, 2020Updated 6 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 4 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Drive a Wishbone master bus with an SPI bus.☆10Apr 24, 2025Updated last year
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Sep 17, 2026Updated last month
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- A synthesizable picmicro-midrange clone for FPGAs☆14Nov 8, 2019Updated 6 years ago
- A project demonstrate how to config ad9361 to TX mode☆13Dec 9, 2018Updated 7 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆31Jun 22, 2018Updated 8 years ago
- A simple script to build open-source FPGA tools.☆55Oct 25, 2022Updated 4 years ago
- axi video dma ip in verilog☆11Aug 22, 2020Updated 6 years ago
- Implementation of FM (frequency modulation) radio transmitter in FPGA Altera Cyclone III.☆14May 16, 2016Updated 10 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆12Jul 20, 2022Updated 4 years ago
- ☆15Dec 19, 2025Updated 10 months ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- VHDL library 4 FPGAs☆187Updated this week
- Library to convert a FASM file into BELs importable into Vivado.☆15Sep 25, 2023Updated 3 years ago
- Motion Estimation implementation by using Verilog HDL☆14Jun 17, 2024Updated 2 years ago
- This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in…☆10Dec 19, 2012Updated 13 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆16Jan 22, 2025Updated last year
- "Simultaneous Localization of Multiple GNSS Interference Sources via Neural Networks" - ION GNSS+ 2017☆13Oct 5, 2018Updated 8 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- cryptography ip-cores in vhdl / verilog☆43Feb 20, 2021Updated 5 years ago
- FPGA-based I2C to RS-232 serial converter / bus monitor☆13Jan 29, 2016Updated 10 years ago
- 1-PPS support for gnss-sdr☆44May 9, 2025Updated last year
- GT-HMI Builder项目是基于GT-HMI的开源硬件系列,涵盖了GT HMI模块(中大尺寸屏)、GUI-LCD开发板(小尺寸屏)、串口屏硬件开源、WIFI SOC开源硬件,本次更新为开发者提供了一套全面的解决方案,从硬件连接到软件配置,再到界面设计,旨在加速理解GT…☆15Mar 25, 2025Updated last year
- A tool for merging the MyHDL workflow with Vivado☆20May 13, 2020Updated 6 years ago
- GPS software-defined receiver (SDR) which acquires and tracks a single GPS L1 C/A signal.☆14Feb 16, 2021Updated 5 years ago
- Documentation for the tinyNX33U SoM and related boards☆13Oct 8, 2026Updated 3 weeks ago