oscimp / fpga_ipLinks
OscillatorIMP ecosystem FPGA IP sources
☆27Updated 2 months ago
Alternatives and similar repositories for fpga_ip
Users that are interested in fpga_ip are comparing it to the libraries listed below
Sorting:
- A collection of Opal Kelly provided design resources☆17Updated 2 months ago
- This is a C library to interface with the LiteX Firmware on Thunderscope over PCIe☆11Updated 3 weeks ago
- Time to Digital Converter (TDC)☆36Updated 5 years ago
- ☆18Updated 5 years ago
- Verilog modules for software-defined radio.☆18Updated 13 years ago
- VHDL PCIe Transceiver☆32Updated 5 years ago
- 基于Kintex-7 XC7K325T的高性能FPGA功能验证板☆18Updated 5 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆14Updated 7 years ago
- Altera Cyclone IV FPGA project for the PCIe LimeSDR board☆42Updated 3 years ago
- ☆20Updated 4 years ago
- LiteX based FPGA gateware for Thunderscope.☆28Updated last month
- ☆16Updated 4 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互,CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程: 1. 链路初始化: 在上位机完成USB固件的下载,并读取…☆29Updated 10 years ago
- an sata controller using smallest resource.☆17Updated 11 years ago
- The implementation of AD9371 on KC705☆20Updated 7 months ago
- VHDL functional blocks with their simulations and test sequences☆20Updated last week
- development interface mil-std-1553b for system on chip☆24Updated 8 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- Verilog FT245 to AXI stream interface☆29Updated 7 years ago
- Small footprint and configurable JESD204B core☆50Updated 2 weeks ago
- An open-source Xilinx Kria SOM Carrier for high-speed camera design☆29Updated 2 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- IP Catalog for Raptor.☆17Updated last year
- JESD204b modules in VHDL☆30Updated 6 years ago
- Testbenches for HDL projects☆22Updated this week
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 4 years ago
- The FPGA design for the FreeSRP's Artix 7 FPGA☆26Updated 8 years ago
- Standalone application based on ADI hdl and no_OS for ANTSDR.☆23Updated 10 months ago