Alternatives and similar repositories for PandABlocks-FPGA

Users that are interested in PandABlocks-FPGA are comparing it to the libraries listed below

• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆13Updated 7 months ago
• oscimp / fpga_ip
  OscillatorIMP ecosystem FPGA IP sources
  ☆27Updated last month
• opalkelly-opensource / design-resources
  A collection of Opal Kelly provided design resources
  ☆16Updated 2 months ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• benreynwar / fpga-sdrlib
  Verilog modules for software-defined radio.
  ☆18Updated 12 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆60Updated 2 years ago
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆21Updated 7 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 2 months ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 7 years ago
• BerkeleyLab / Marble-Mini
  "Marble-Mini" Simple FMC carrier board with SFP, 2x FMC, PoE
  ☆18Updated 3 years ago
• OpenAutomationTechnologies / VHDL_IP-Cores
  ☆17Updated 4 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆28Updated 4 years ago
• nandland / memory
  Single Port RAM, Dual Port RAM, FIFO
  ☆24Updated 3 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated 3 weeks ago
• BrianHGinc / Verilog-Floating-Point-Clock-Divider
  Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…
  ☆19Updated 3 months ago
• necst / zynq_userspace_dma
  Userspace DMA library for Zynq-based SoCs
  ☆16Updated 6 years ago
• VideoGPU / FMC_MIPI
  FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface
  ☆17Updated 2 years ago
• jsyk / miilink
  Connecting FPGA and MCU using Ethernet RMII
  ☆23Updated 9 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 4 years ago
• lewiz-support / LMAC_CORE1
  LMAC Core1 - Ethernet 1G/100M/10M
  ☆16Updated 2 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆30Updated 4 years ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• KindaM3h / SpaceVNXBaseBoard
  SpaceVNX (VITA 74.4) carrier based on Zynq-7000.
  ☆13Updated 2 years ago
• esynr3z / adc-eval
  📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC
  ☆20Updated last year
• gtortone / libaxidma
  C++ library for AXI DMA with direct and scatter-gather support
  ☆10Updated 3 years ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 12 years ago
• juliancoy / openStreamHDL
  VHDL Code for infrastructural blocks (designed for FPGA)
  ☆15Updated 2 years ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆16Updated this week
• phthinh / OFDM_802_16
  IEEE 802.16 OFDM-based transceiver system
  ☆23Updated 5 years ago