PandABlocks / PandABlocks-FPGALinks
VHDL functional blocks with their simulations and test sequences
☆20Updated last week
Alternatives and similar repositories for PandABlocks-FPGA
Users that are interested in PandABlocks-FPGA are comparing it to the libraries listed below
Sorting:
- A collection of Opal Kelly provided design resources☆17Updated 2 weeks ago
- GSI Timing Gateware and Tools☆14Updated this week
- Repository containing the DSP gateware cores☆13Updated last week
- Verilog modules for software-defined radio.☆18Updated 12 years ago
- general-cores☆20Updated last month
- LMAC Core1 - Ethernet 1G/100M/10M☆17Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆34Updated 6 months ago
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆21Updated 2 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Testbenches for HDL projects☆20Updated last week
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- OscillatorIMP ecosystem FPGA IP sources☆28Updated last month
- Fixed-point math library with VHDL, Python and MATLAB support☆27Updated 2 weeks ago
- Example designs for using Ethernet FMC without a processor (ie. state machine based)☆31Updated 9 months ago
- ☆18Updated 4 years ago
- development interface mil-std-1553b for system on chip☆22Updated 7 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆18Updated 2 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆12Updated 5 years ago
- Time to Digital Converter (TDC)☆31Updated 4 years ago
- ☆17Updated last year
- VHDL PCIe Transceiver☆30Updated 5 years ago
- Open FPGA Modules☆24Updated 10 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆64Updated 2 weeks ago
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- ☆17Updated 4 years ago