PandABlocks / PandABlocks-FPGALinks
VHDL functional blocks with their simulations and test sequences
☆21Updated this week
Alternatives and similar repositories for PandABlocks-FPGA
Users that are interested in PandABlocks-FPGA are comparing it to the libraries listed below
Sorting:
- Repository containing the DSP gateware cores☆13Updated last week
- OscillatorIMP ecosystem FPGA IP sources☆28Updated last week
- A collection of Opal Kelly provided design resources☆16Updated 3 months ago
- Verilog modules for software-defined radio.☆18Updated 12 years ago
- ☆17Updated 4 years ago
- GSI Timing Gateware and Tools☆14Updated this week
- "Marble-Mini" Simple FMC carrier board with SFP, 2x FMC, PoE☆19Updated 3 years ago
- SpaceVNX (VITA 74.4) carrier based on Zynq-7000.☆13Updated 2 years ago
- This is a C library to interface with the LiteX Firmware on Thunderscope over PCIe☆11Updated 2 weeks ago
- an sata controller using smallest resource.☆16Updated 11 years ago
- development interface mil-std-1553b for system on chip☆21Updated 7 years ago
- Demonstration of Automatic Gain Control with PYNQ☆14Updated 2 years ago
- Testbenches for HDL projects☆18Updated last week
- IP Catalog for Raptor.☆13Updated 6 months ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 4 months ago
- VHDL PCIe Transceiver☆28Updated 4 years ago
- 利用ZYNQ7020实现SAR数据采集系统,其中包含硬件设计代码、上位机、测试程序。☆11Updated 4 months ago
- Small footprint and configurable JESD204B core☆44Updated last month
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- An RFSoC Frequency Planner developed using Python.☆28Updated 2 years ago
- Adapter board exposing SATA M.2 SSD on FMC board-to-board connector☆12Updated last year
- SLAC Python Based Hardware Abstraction & Data Acquisition System☆46Updated 3 weeks ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆60Updated this week
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆22Updated 9 years ago
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆14Updated 4 years ago
- C++ library for AXI DMA with direct and scatter-gather support☆10Updated 3 years ago
- 基于Kintex-7 XC7K325T的高性能FPGA功能验证板☆19Updated 5 years ago
- Zest is a FMC mezzanine board with 8 ADC channels and 2 DACs☆11Updated 7 months ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year