opalkelly-opensource / design-resourcesLinks
A collection of Opal Kelly provided design resources
☆17Updated 2 months ago
Alternatives and similar repositories for design-resources
Users that are interested in design-resources are comparing it to the libraries listed below
Sorting:
- general-cores☆21Updated 3 months ago
- Testbenches for HDL projects☆21Updated last week
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago
- OscillatorIMP ecosystem FPGA IP sources☆27Updated 3 months ago
- GSI Timing Gateware and Tools☆14Updated this week
- JESD204b modules in VHDL☆30Updated 6 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- IP Catalog for Raptor.☆16Updated 10 months ago
- VHDL functional blocks with their simulations and test sequences☆20Updated this week
- development interface mil-std-1553b for system on chip☆23Updated 7 years ago
- LMAC Core1 - Ethernet 1G/100M/10M☆18Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆35Updated 8 months ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆11Updated 7 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- ☆18Updated 2 years ago
- Open FPGA Modules☆24Updated last year
- Trying to learn Wishbone by implementing few master/slave devices☆13Updated 6 years ago
- ☆19Updated 4 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- Xilinx IP repository☆13Updated 7 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- Time to Digital Converter (TDC)☆34Updated 4 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- SPI-Flash XIP Interface (Verilog)☆45Updated 4 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆20Updated 8 months ago
- UART to AXI Stream interface written in VHDL☆17Updated 3 years ago
- ☆30Updated 8 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆66Updated 3 weeks ago
- An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components☆46Updated 4 years ago