A collection of Opal Kelly provided design resources
☆19Jun 15, 2026Updated last month
Alternatives and similar repositories for design-resources
Users that are interested in design-resources are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Miscellaneous things and projects for my ZYBO and ZYNQ devices.☆11Aug 30, 2023Updated 2 years ago
- Collection of hardware description languages writings and code snippets☆30Jan 29, 2015Updated 11 years ago
- Present Crypto Engine in Verilog☆12Feb 27, 2016Updated 10 years ago
- ☆19Sep 14, 2025Updated 10 months ago
- 使用DDS芯片AD9914产生线性扫频信号☆12Dec 9, 2020Updated 5 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- ☆17Apr 25, 2024Updated 2 years ago
- Synthesizable Higher-Order Functions (Patterns) for C++☆18Oct 3, 2018Updated 7 years ago
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆30Mar 24, 2021Updated 5 years ago
- Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1☆40Feb 18, 2024Updated 2 years ago
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- Half-precision floating point for NumPy☆13Nov 10, 2010Updated 15 years ago
- HDL and software samples for interfacing the XEM7320 with various SYZYGY peripherals.☆13Nov 14, 2019Updated 6 years ago
- general-cores☆21Jul 16, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 5 months ago
- A basic documentation generator for Verilog, similar to Doxygen.☆13Aug 5, 2016Updated 10 years ago
- VHDL Library for implementing common DSP functionality.☆33Oct 5, 2018Updated 7 years ago
- Example Projects for the Microsemi SmartFusion 2☆11Dec 10, 2017Updated 8 years ago
- Triple Modular Redundancy☆31Sep 4, 2019Updated 6 years ago
- Library for reading Xilinx .bit bitstream file headers with metadata extraction☆14Apr 7, 2026Updated 4 months ago
- JESD204b modules in VHDL☆30Apr 18, 2019Updated 7 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆36Aug 7, 2021Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- softfloat and softposit in Python☆15Aug 2, 2019Updated 7 years ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 4 years ago
- Small (Q)SPI flash memory programmer in Verilog☆70Nov 5, 2022Updated 3 years ago
- MAC system with IEEE754 compatibility☆14Nov 22, 2023Updated 2 years ago
- This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL☆28Oct 4, 2021Updated 4 years ago
- Open source FPGA cores for digital signal processing (push mirror from gitlab.com/theseus-cores/theseus-cores)☆16Aug 16, 2021Updated 4 years ago
- Synchronous use of two LS7366R decoders on Arduino env☆11Sep 9, 2014Updated 11 years ago
- high level VHDL floating point library for synthesis in fpga☆18Dec 18, 2025Updated 7 months ago
- 基于FP16的二维脉动阵列电路设计☆13Feb 23, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- AMD University Program HLS tutorial☆131Oct 28, 2024Updated last year
- Nengo extension to connect to FPGAs☆18Aug 2, 2026Updated last week
- Tutorial on how to use the AXI ACP on the UltraZed-EG IOCC☆11Jun 13, 2018Updated 8 years ago
- SQRL FK33 board files, example designs and scripts.☆20Nov 7, 2022Updated 3 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆20Dec 5, 2014Updated 11 years ago
- 🏆 Amazon Best Seller | Full-stack AI NPU Design (Python, Verilog, ISA, FPGA) Vol.2 Coming Soon!☆24Mar 3, 2026Updated 5 months ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆40Jun 10, 2026Updated 2 months ago