Alternatives and similar repositories for design-resources

Users that are interested in design-resources are comparing it to the libraries listed below

• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆22Updated this week
• lnls-dig / general-cores
  general-cores
  ☆21Updated 6 months ago
• lewiz-support / LMAC_CORE1
  LMAC Core1 - Ethernet 1G/100M/10M
  ☆19Updated 2 years ago
• Digilent / axi4lite_ip_gen
  Generates simple AXI4-lite IP for use in Vivado from register specifications
  ☆15Updated 9 months ago
• CESNET / ofm
  Open FPGA Modules
  ☆24Updated last year
• PandABlocks / PandABlocks-FPGA
  VHDL functional blocks with their simulations and test sequences
  ☆20Updated this week
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆18Updated 3 years ago
• os-fpga / IP_Catalog
  IP Catalog for Raptor.
  ☆17Updated last year
• viktor-nikolov / Zynq-XADC-DMA-lwIP
  Tutorial for analog input digitalization by the Xilinx Zynq XADC utilizing the DMA and data streaming to a PC over the network.
  ☆30Updated 4 months ago
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆15Updated 2 months ago
• GSI-CS-CO / bel_projects
  GSI Timing Gateware and Tools
  ☆14Updated this week
• benreynwar / fpga-sdrlib
  Verilog modules for software-defined radio.
  ☆18Updated 13 years ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated 2 years ago
• LukiLeu / FPGA_ADC
  An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components
  ☆46Updated 4 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆39Updated 11 months ago
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆29Updated 5 years ago
• patocarr / axi-traffic-gen
  File editor for the Xilinx AXI Traffic Generator IP
  ☆16Updated last year
• FDU-ME-ARC / NVMeCHA
  ☆20Updated 4 years ago
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆24Updated 7 years ago
• semahawk / wishbone
  Trying to learn Wishbone by implementing few master/slave devices
  ☆13Updated 7 years ago
• BrianHGinc / Verilog-Floating-Point-Clock-Divider
  Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…
  ☆21Updated 11 months ago
• vfinotti / ahb3lite_wb_bridge
  AHB3-Lite to Wishbone Bridge
  ☆13Updated 6 years ago
• coralhu123 / KC705-AD9371
  The implementation of AD9371 on KC705
  ☆20Updated 7 months ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆36Updated 5 years ago
• esynr3z / adc-eval
  📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC
  ☆23Updated 2 years ago
• chinkwo / FPGA-multiboot
  通过SPI协议实现FPGA multiboot在线升级功能
  ☆12Updated 7 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 7 years ago
• hVHDL / hVHDL_floating_point
  high level VHDL floating point library for synthesis in fpga
  ☆18Updated last month