joelagnel / i2c-master
An i2c master controller implemented in Verilog
☆31Updated 7 years ago
Alternatives and similar repositories for i2c-master:
Users that are interested in i2c-master are comparing it to the libraries listed below
- UART -> AXI Bridge☆60Updated 3 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated 11 months ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆32Updated 3 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Verilog SPI master and slave☆52Updated 9 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆22Updated 2 years ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- USB 2.0 Device IP Core☆65Updated 7 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆51Updated 4 years ago
- I2C controller core☆39Updated 2 years ago
- Small (Q)SPI flash memory programmer in Verilog☆61Updated 2 years ago
- Generator for CRC HDL code (VHDL, Verilog, MyHDL)☆33Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 10 years ago
- SPI-Flash XIP Interface (Verilog)☆36Updated 3 years ago
- ☆30Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- UART 16550 core☆34Updated 10 years ago
- Reed Solomon Decoder (204,188)☆12Updated 10 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆146Updated last month
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- DDR2 memory controller written in Verilog☆76Updated 13 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 10 months ago
- ☆61Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆76Updated 11 months ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 5 years ago