An i2c master controller implemented in Verilog
☆34Jul 26, 2017Updated 8 years ago
Alternatives and similar repositories for i2c-master
Users that are interested in i2c-master are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog I2C Slave☆24Aug 11, 2014Updated 11 years ago
- Verilog Code for I2C Protocol☆19Nov 12, 2020Updated 5 years ago
- I2C Master Verilog module☆38Jun 1, 2025Updated 10 months ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆27Mar 9, 2016Updated 10 years ago
- Zedboard projects☆11May 15, 2016Updated 9 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆19Dec 5, 2014Updated 11 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 8 years ago
- Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable☆27Mar 3, 2026Updated last month
- Verilog example programs for TinyFPGA☆24Nov 8, 2019Updated 6 years ago
- Simple implementation of I2C interface written on Verilog and SystemC☆49Aug 26, 2017Updated 8 years ago
- Mirror of NeTV FPGA Verilog Code☆15Jan 21, 2012Updated 14 years ago
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago
- Basic Data Structure Algorithm in C++☆13Nov 4, 2022Updated 3 years ago
- Discrete Cosine Transform (DCT) is one of the important image compression algorithms used in image processing applications. Several algor…☆26May 5, 2015Updated 10 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Generic Logic Interfacing Project☆49Jul 29, 2020Updated 5 years ago
- Simple strutured VERILOG netlist to SPICE netlist translator☆25May 22, 2022Updated 3 years ago
- An OpenFlow implementation for the NetFPGA-10G card☆19Feb 18, 2015Updated 11 years ago
- hdmi-ts Project☆13Jun 11, 2017Updated 8 years ago
- 400 nm SiO2 capacitor simulation of interface trap formation with state transitions in Sentaurus TCAD☆15May 26, 2017Updated 8 years ago
- HAT for Raspberry Pi with TAS5825M stereo amplifier, 30W RMS per channel☆11Apr 16, 2024Updated 2 years ago
- USB -> AXI Debug Bridge☆43Jun 5, 2021Updated 4 years ago
- 8b/10b is a line code that maps 8-bit words to 10-bit symbols to achieve DC-balance and bounded disparity, which is used for telecommunic…☆12Jun 8, 2021Updated 4 years ago
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- AXI总线连接器☆105Mar 26, 2020Updated 6 years ago
- hostmot2 firmware for the embedded micro mojo v3 fpga☆11Mar 29, 2020Updated 6 years ago
- Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)☆15Sep 5, 2023Updated 2 years ago
- ☆10Oct 25, 2022Updated 3 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Jul 17, 2014Updated 11 years ago
- HDMI + GPU-pipeline + FFT☆14Mar 4, 2016Updated 10 years ago
- Design and simulate a simplified ARM single-cycle processor using SystemVerilog.☆10Sep 13, 2019Updated 6 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- Picorv32 SoC on the TinyFPGA BX, for games etc.☆12Sep 22, 2018Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- hardware implement of huffman coding(written in verilog)☆14Jul 30, 2017Updated 8 years ago
- ☆27Jun 12, 2022Updated 3 years ago
- Getting started with rust on picosoc☆14Feb 27, 2023Updated 3 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- FPGA controller for SSD1306 OLED module on SPI. Optimised for GOWIN FPGA☆15Oct 11, 2018Updated 7 years ago
- Uart module written in chisel☆13Feb 19, 2016Updated 10 years ago